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[PATCH v5 05/13] target/riscv: Make RLB/MML/MMWP bits writable only when
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From: |
Weiwei Li |
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Subject: |
[PATCH v5 05/13] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled |
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Date: |
Fri, 28 Apr 2023 22:36:13 +0800 |
RLB/MML/MMWP bits in mseccfg CSR are introduced by Smepmp extension.
So they can only be writable and set to 1s when cfg.epmp is true.
Then we also need't check on epmp in pmp_hart_has_privs_default().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/pmp.c | 50 ++++++++++++++++++++++++----------------------
1 file changed, 26 insertions(+), 24 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index b5808538aa..e745842973 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -243,30 +243,28 @@ static bool pmp_hart_has_privs_default(CPURISCVState
*env, target_ulong addr,
{
bool ret;
- if (riscv_cpu_cfg(env)->epmp) {
- if (MSECCFG_MMWP_ISSET(env)) {
- /*
- * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
- * so we default to deny all, even for M-mode.
- */
+ if (MSECCFG_MMWP_ISSET(env)) {
+ /*
+ * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
+ * so we default to deny all, even for M-mode.
+ */
+ *allowed_privs = 0;
+ return false;
+ } else if (MSECCFG_MML_ISSET(env)) {
+ /*
+ * The Machine Mode Lockdown (mseccfg.MML) bit is set
+ * so we can only execute code in M-mode with an applicable
+ * rule. Other modes are disabled.
+ */
+ if (mode == PRV_M && !(privs & PMP_EXEC)) {
+ ret = true;
+ *allowed_privs = PMP_READ | PMP_WRITE;
+ } else {
+ ret = false;
*allowed_privs = 0;
- return false;
- } else if (MSECCFG_MML_ISSET(env)) {
- /*
- * The Machine Mode Lockdown (mseccfg.MML) bit is set
- * so we can only execute code in M-mode with an applicable
- * rule. Other modes are disabled.
- */
- if (mode == PRV_M && !(privs & PMP_EXEC)) {
- ret = true;
- *allowed_privs = PMP_READ | PMP_WRITE;
- } else {
- ret = false;
- *allowed_privs = 0;
- }
-
- return ret;
}
+
+ return ret;
}
if (!riscv_cpu_cfg(env)->pmp || (mode == PRV_M)) {
@@ -580,8 +578,12 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong
val)
}
}
- /* Sticky bits */
- val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+ if (riscv_cpu_cfg(env)->epmp) {
+ /* Sticky bits */
+ val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+ } else {
+ val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
+ }
env->mseccfg = val;
}
--
2.25.1
- [PATCH v5 00/13] target/riscv: Fix PMP related problem, Weiwei Li, 2023/04/28
- [PATCH v5 02/13] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp, Weiwei Li, 2023/04/28
- [PATCH v5 07/13] target/riscv: Flush TLB when MMWP or MML bits are changed, Weiwei Li, 2023/04/28
- [PATCH v5 04/13] target/riscv: Change the return type of pmp_hart_has_privs() to bool, Weiwei Li, 2023/04/28
- [PATCH v5 03/13] target/riscv: Make the short cut really work in pmp_hart_has_privs, Weiwei Li, 2023/04/28
- [PATCH v5 06/13] target/riscv: Remove unused paramters in pmp_hart_has_privs_default(), Weiwei Li, 2023/04/28
- [PATCH v5 05/13] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled,
Weiwei Li <=
- [PATCH v5 01/13] target/riscv: Update pmp_get_tlb_size(), Weiwei Li, 2023/04/28
- [PATCH v5 10/13] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes, Weiwei Li, 2023/04/28
- [PATCH v5 08/13] target/riscv: Update the next rule addr in pmpaddr_csr_write(), Weiwei Li, 2023/04/28
- [PATCH v5 13/13] target/riscv: Deny access if access is partially inside the PMP entry, Weiwei Li, 2023/04/28
- [PATCH v5 12/13] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write, Weiwei Li, 2023/04/28
- [PATCH v5 11/13] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1, Weiwei Li, 2023/04/28
- [PATCH v5 09/13] target/riscv: Flush TLB when pmpaddr is updated, Weiwei Li, 2023/04/28