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[PATCH v5 09/13] target/riscv: Flush TLB when pmpaddr is updated
From: |
Weiwei Li |
Subject: |
[PATCH v5 09/13] target/riscv: Flush TLB when pmpaddr is updated |
Date: |
Fri, 28 Apr 2023 22:36:17 +0800 |
TLB should be flushed not only for pmpcfg csr changes, but also for
pmpaddr csr changes.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/pmp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 3af2caff31..5627e9fe70 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -531,6 +531,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t
addr_index,
if (is_next_cfg_tor) {
pmp_update_rule_addr(env, addr_index + 1);
}
+ tlb_flush(env_cpu(env));
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - locked\n");
--
2.25.1
- [PATCH v5 04/13] target/riscv: Change the return type of pmp_hart_has_privs() to bool, (continued)
- [PATCH v5 04/13] target/riscv: Change the return type of pmp_hart_has_privs() to bool, Weiwei Li, 2023/04/28
- [PATCH v5 03/13] target/riscv: Make the short cut really work in pmp_hart_has_privs, Weiwei Li, 2023/04/28
- [PATCH v5 06/13] target/riscv: Remove unused paramters in pmp_hart_has_privs_default(), Weiwei Li, 2023/04/28
- [PATCH v5 05/13] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled, Weiwei Li, 2023/04/28
- [PATCH v5 01/13] target/riscv: Update pmp_get_tlb_size(), Weiwei Li, 2023/04/28
- [PATCH v5 10/13] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes, Weiwei Li, 2023/04/28
- [PATCH v5 08/13] target/riscv: Update the next rule addr in pmpaddr_csr_write(), Weiwei Li, 2023/04/28
- [PATCH v5 13/13] target/riscv: Deny access if access is partially inside the PMP entry, Weiwei Li, 2023/04/28
- [PATCH v5 12/13] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write, Weiwei Li, 2023/04/28
- [PATCH v5 11/13] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1, Weiwei Li, 2023/04/28
- [PATCH v5 09/13] target/riscv: Flush TLB when pmpaddr is updated,
Weiwei Li <=