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[PATCH 12/12] tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN
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From: |
Richard Henderson |
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Subject: |
[PATCH 12/12] tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN |
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Date: |
Fri, 7 Apr 2023 20:03:59 -0700 |
Since e03b56863d2b, which replaced HOST_WORDS_BIGENDIAN
with HOST_BIG_ENDIAN, there is no need to define a second
symbol which is [0,1].
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 88 ++++++++++++++++++---------------------
1 file changed, 41 insertions(+), 47 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 1df00bf027..9767065af0 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -27,14 +27,8 @@
#include "../tcg-ldst.c.inc"
#include "../tcg-pool.c.inc"
-#if HOST_BIG_ENDIAN
-# define MIPS_BE 1
-#else
-# define MIPS_BE 0
-#endif
-
#if TCG_TARGET_REG_BITS == 32
-# define LO_OFF (MIPS_BE * 4)
+# define LO_OFF (HOST_BIG_ENDIAN * 4)
# define HI_OFF (4 - LO_OFF)
#else
/* Assert at compile-time that these values are never used for 64-bit. */
@@ -1354,7 +1348,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,
TCGLabelQemuLdst *l)
if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
/* We eliminated V0 from the possible output registers, so it
cannot be clobbered here. So we must move V1 first. */
- if (MIPS_BE) {
+ if (HOST_BIG_ENDIAN) {
tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1);
v0 = l->datahi_reg;
} else {
@@ -1438,8 +1432,8 @@ static bool tcg_out_fail_alignment(TCGContext *s,
TCGLabelQemuLdst *l)
if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
/* A0 is env, A1 is skipped, A2:A3 is the uint64_t address. */
- TCGReg a2 = MIPS_BE ? l->addrhi_reg : l->addrlo_reg;
- TCGReg a3 = MIPS_BE ? l->addrlo_reg : l->addrhi_reg;
+ TCGReg a2 = HOST_BIG_ENDIAN ? l->addrhi_reg : l->addrlo_reg;
+ TCGReg a3 = HOST_BIG_ENDIAN ? l->addrlo_reg : l->addrhi_reg;
if (a3 != TCG_REG_A2) {
tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2);
@@ -1551,8 +1545,8 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg
lo, TCGReg hi,
tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
- tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
- tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
+ tcg_out_opc_sa(s, OPC_ROTR, HOST_BIG_ENDIAN ? lo : hi, TCG_TMP0,
16);
+ tcg_out_opc_sa(s, OPC_ROTR, HOST_BIG_ENDIAN ? hi : lo, TCG_TMP1,
16);
} else {
tcg_out_bswap_subr(s, bswap32_addr);
/* delay slot */
@@ -1560,15 +1554,15 @@ static void tcg_out_qemu_ld_direct(TCGContext *s,
TCGReg lo, TCGReg hi,
tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4);
tcg_out_bswap_subr(s, bswap32_addr);
/* delay slot */
- tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
- tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
+ tcg_out_mov(s, TCG_TYPE_I32, HOST_BIG_ENDIAN ? lo : hi, TCG_TMP3);
+ tcg_out_mov(s, TCG_TYPE_I32, HOST_BIG_ENDIAN ? hi : lo, TCG_TMP3);
}
break;
case MO_UQ:
/* Prefer to load from offset 0 first, but allow for overlap. */
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
- } else if (MIPS_BE ? hi != base : lo == base) {
+ } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) {
tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
} else {
@@ -1584,10 +1578,10 @@ static void tcg_out_qemu_ld_direct(TCGContext *s,
TCGReg lo, TCGReg hi,
static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
TCGReg base, MemOp opc, TCGType type)
{
- const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR;
- const MIPSInsn lw2 = MIPS_BE ? OPC_LWR : OPC_LWL;
- const MIPSInsn ld1 = MIPS_BE ? OPC_LDL : OPC_LDR;
- const MIPSInsn ld2 = MIPS_BE ? OPC_LDR : OPC_LDL;
+ const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR;
+ const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL;
+ const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR;
+ const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL;
bool sgn = (opc & MO_SIGN);
@@ -1653,10 +1647,10 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s,
TCGReg lo, TCGReg hi,
tcg_out_opc_imm(s, ld1, lo, base, 0);
tcg_out_opc_imm(s, ld2, lo, base, 7);
} else {
- tcg_out_opc_imm(s, lw1, MIPS_BE ? hi : lo, base, 0 + 0);
- tcg_out_opc_imm(s, lw2, MIPS_BE ? hi : lo, base, 0 + 3);
- tcg_out_opc_imm(s, lw1, MIPS_BE ? lo : hi, base, 4 + 0);
- tcg_out_opc_imm(s, lw2, MIPS_BE ? lo : hi, base, 4 + 3);
+ tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0);
+ tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3);
+ tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0);
+ tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3);
}
break;
@@ -1680,19 +1674,19 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s,
TCGReg lo, TCGReg hi,
tcg_out_opc_imm(s, lw2, TCG_TMP1, base, 4 + 3);
tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
- tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
- tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
+ tcg_out_opc_sa(s, OPC_ROTR, HOST_BIG_ENDIAN ? lo : hi, TCG_TMP0,
16);
+ tcg_out_opc_sa(s, OPC_ROTR, HOST_BIG_ENDIAN ? hi : lo, TCG_TMP1,
16);
} else {
tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0);
tcg_out_bswap_subr(s, bswap32_addr);
/* delay slot */
tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3);
tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 4 + 0);
- tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
+ tcg_out_mov(s, TCG_TYPE_I32, HOST_BIG_ENDIAN ? lo : hi, TCG_TMP3);
tcg_out_bswap_subr(s, bswap32_addr);
/* delay slot */
tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 4 + 3);
- tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
+ tcg_out_mov(s, TCG_TYPE_I32, HOST_BIG_ENDIAN ? hi : lo, TCG_TMP3);
}
break;
@@ -1802,16 +1796,16 @@ static void tcg_out_qemu_st_direct(TCGContext *s,
TCGReg lo, TCGReg hi,
tcg_out_bswap64(s, TCG_TMP3, lo);
tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);
} else if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
- tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
+ tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, HOST_BIG_ENDIAN ? lo :
hi);
+ tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, HOST_BIG_ENDIAN ? hi :
lo);
tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
} else {
- tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0);
+ tcg_out_bswap32(s, TCG_TMP3, HOST_BIG_ENDIAN ? lo : hi, 0);
tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
- tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0);
+ tcg_out_bswap32(s, TCG_TMP3, HOST_BIG_ENDIAN ? hi : lo, 0);
tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
}
break;
@@ -1819,8 +1813,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg
lo, TCGReg hi,
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
} else {
- tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
- tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
+ tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0);
+ tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4);
}
break;
@@ -1832,10 +1826,10 @@ static void tcg_out_qemu_st_direct(TCGContext *s,
TCGReg lo, TCGReg hi,
static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
TCGReg base, MemOp opc)
{
- const MIPSInsn sw1 = MIPS_BE ? OPC_SWL : OPC_SWR;
- const MIPSInsn sw2 = MIPS_BE ? OPC_SWR : OPC_SWL;
- const MIPSInsn sd1 = MIPS_BE ? OPC_SDL : OPC_SDR;
- const MIPSInsn sd2 = MIPS_BE ? OPC_SDR : OPC_SDL;
+ const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR;
+ const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL;
+ const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR;
+ const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL;
/* Don't clutter the code below with checks to avoid bswapping ZERO. */
if ((lo | hi) == 0) {
@@ -1869,17 +1863,17 @@ static void tcg_out_qemu_st_unalign(TCGContext *s,
TCGReg lo, TCGReg hi,
tcg_out_bswap64(s, TCG_TMP3, lo);
lo = TCG_TMP3;
} else if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? hi : lo);
- tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? lo : hi);
+ tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, HOST_BIG_ENDIAN ? hi :
lo);
+ tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, HOST_BIG_ENDIAN ? lo :
hi);
tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
- hi = MIPS_BE ? TCG_TMP0 : TCG_TMP1;
- lo = MIPS_BE ? TCG_TMP1 : TCG_TMP0;
+ hi = HOST_BIG_ENDIAN ? TCG_TMP0 : TCG_TMP1;
+ lo = HOST_BIG_ENDIAN ? TCG_TMP1 : TCG_TMP0;
} else {
- tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0);
+ tcg_out_bswap32(s, TCG_TMP3, HOST_BIG_ENDIAN ? lo : hi, 0);
tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 0 + 0);
tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 0 + 3);
- tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0);
+ tcg_out_bswap32(s, TCG_TMP3, HOST_BIG_ENDIAN ? hi : lo, 0);
tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 4 + 0);
tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 4 + 3);
break;
@@ -1890,10 +1884,10 @@ static void tcg_out_qemu_st_unalign(TCGContext *s,
TCGReg lo, TCGReg hi,
tcg_out_opc_imm(s, sd1, lo, base, 0);
tcg_out_opc_imm(s, sd2, lo, base, 7);
} else {
- tcg_out_opc_imm(s, sw1, MIPS_BE ? hi : lo, base, 0 + 0);
- tcg_out_opc_imm(s, sw2, MIPS_BE ? hi : lo, base, 0 + 3);
- tcg_out_opc_imm(s, sw1, MIPS_BE ? lo : hi, base, 4 + 0);
- tcg_out_opc_imm(s, sw2, MIPS_BE ? lo : hi, base, 4 + 3);
+ tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0);
+ tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3);
+ tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0);
+ tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3);
}
break;
--
2.34.1
- [PATCH 01/12] tcg/mips: Move TCG_AREG0 to S8, (continued)
- [PATCH 01/12] tcg/mips: Move TCG_AREG0 to S8, Richard Henderson, 2023/04/07
- [PATCH 03/12] tcg/mips: Unify TCG_GUEST_BASE_REG tests, Richard Henderson, 2023/04/07
- [PATCH 05/12] tcg/mips: Split out tcg_out_movi_one, Richard Henderson, 2023/04/07
- [PATCH 09/12] tcg/mips: Try tb-relative addresses in tcg_out_movi, Richard Henderson, 2023/04/07
- [PATCH 10/12] tcg/mips: Try three insns with shift and add in tcg_out_movi, Richard Henderson, 2023/04/07
- [PATCH 08/12] tcg/mips: Aggressively use the constant pool for n64 calls, Richard Henderson, 2023/04/07
- [PATCH 07/12] tcg/mips: Use the constant pool for 64-bit constants, Richard Henderson, 2023/04/07
- [PATCH 12/12] tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN,
Richard Henderson <=
- [PATCH 11/12] tcg/mips: Use qemu_build_not_reached for LO/HI_OFF, Richard Henderson, 2023/04/07
- [PATCH 04/12] tcg/mips: Create and use TCG_REG_TB, Richard Henderson, 2023/04/07
- [PATCH 06/12] tcg/mips: Split out tcg_out_movi_two, Richard Henderson, 2023/04/07