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[PATCH 07/12] tcg/mips: Use the constant pool for 64-bit constants
From: |
Richard Henderson |
Subject: |
[PATCH 07/12] tcg/mips: Use the constant pool for 64-bit constants |
Date: |
Fri, 7 Apr 2023 20:03:54 -0700 |
During normal processing, the constant pool is accessible via
TCG_REG_TB. During the prologue, it is accessible via TCG_REG_T9.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.h | 1 +
tcg/mips/tcg-target.c.inc | 65 +++++++++++++++++++++++++++++----------
2 files changed, 49 insertions(+), 17 deletions(-)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 8cdc803523..88a8137bcc 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -207,5 +207,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_MEMORY_BSWAP 1
#define TCG_TARGET_NEED_LDST_LABELS
+#define TCG_TARGET_NEED_POOL_LABELS
#endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 78710a25bf..235295c689 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -25,6 +25,7 @@
*/
#include "../tcg-ldst.c.inc"
+#include "../tcg-pool.c.inc"
#if HOST_BIG_ENDIAN
# define MIPS_BE 1
@@ -168,9 +169,18 @@ static bool reloc_pc16(tcg_insn_unit *src_rw, const
tcg_insn_unit *target)
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend)
{
- tcg_debug_assert(type == R_MIPS_PC16);
- tcg_debug_assert(addend == 0);
- return reloc_pc16(code_ptr, (const tcg_insn_unit *)value);
+ value += addend;
+ switch (type) {
+ case R_MIPS_PC16:
+ return reloc_pc16(code_ptr, (const tcg_insn_unit *)value);
+ case R_MIPS_16:
+ if (value != (int16_t)value) {
+ return false;
+ }
+ *code_ptr = deposit32(*code_ptr, 0, 16, value);
+ return true;
+ }
+ g_assert_not_reached();
}
#define TCG_CT_CONST_ZERO 0x100
@@ -490,6 +500,11 @@ static void tcg_out_nop(TCGContext *s)
tcg_out32(s, 0);
}
+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+{
+ memset(p, 0, count * sizeof(tcg_insn_unit));
+}
+
static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
{
tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
@@ -547,8 +562,15 @@ static bool tcg_out_movi_two(TCGContext *s, TCGReg ret,
tcg_target_long arg)
return false;
}
-static void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long arg)
+static void tcg_out_movi_pool(TCGContext *s, TCGReg ret,
+ tcg_target_long arg, TCGReg tbreg)
+{
+ new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL));
+ tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0);
+}
+
+static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
+ tcg_target_long arg, TCGReg tbreg)
{
if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
arg = (int32_t)arg;
@@ -558,18 +580,17 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
if (tcg_out_movi_two(s, ret, arg)) {
return;
}
+ assert(TCG_TARGET_REG_BITS == 64);
- tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
- if (arg & 0xffff0000ull) {
- tcg_out_dsll(s, ret, ret, 16);
- tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
- tcg_out_dsll(s, ret, ret, 16);
- } else {
- tcg_out_dsll(s, ret, ret, 32);
- }
- if (arg & 0xffff) {
- tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
- }
+ /* Otherwise, put 64-bit constants into the constant pool. */
+ tcg_out_movi_pool(s, ret, arg, tbreg);
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
+{
+ TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0;
+ tcg_out_movi_int(s, type, ret, arg, tbreg);
}
static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
@@ -2693,10 +2714,20 @@ static void tcg_target_qemu_prologue(TCGContext *s)
#ifndef CONFIG_SOFTMMU
if (guest_base != (int16_t)guest_base) {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
+ /*
+ * The function call abi for n32 and n64 will have loaded $25 (t9)
+ * with the address of the prologue, so we can use that instead
+ * of TCG_REG_TB.
+ */
+#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls)
+# error "Unknown mips abi"
+#endif
+ tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base,
+ TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0);
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
}
#endif
+
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
}
--
2.34.1
- [PATCH 02/12] tcg/mips: Move TCG_GUEST_BASE_REG to S7, (continued)
- [PATCH 02/12] tcg/mips: Move TCG_GUEST_BASE_REG to S7, Richard Henderson, 2023/04/07
- [PATCH 01/12] tcg/mips: Move TCG_AREG0 to S8, Richard Henderson, 2023/04/07
- [PATCH 03/12] tcg/mips: Unify TCG_GUEST_BASE_REG tests, Richard Henderson, 2023/04/07
- [PATCH 05/12] tcg/mips: Split out tcg_out_movi_one, Richard Henderson, 2023/04/07
- [PATCH 09/12] tcg/mips: Try tb-relative addresses in tcg_out_movi, Richard Henderson, 2023/04/07
- [PATCH 10/12] tcg/mips: Try three insns with shift and add in tcg_out_movi, Richard Henderson, 2023/04/07
- [PATCH 08/12] tcg/mips: Aggressively use the constant pool for n64 calls, Richard Henderson, 2023/04/07
- [PATCH 07/12] tcg/mips: Use the constant pool for 64-bit constants,
Richard Henderson <=
- [PATCH 12/12] tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN, Richard Henderson, 2023/04/07
- [PATCH 11/12] tcg/mips: Use qemu_build_not_reached for LO/HI_OFF, Richard Henderson, 2023/04/07
- [PATCH 04/12] tcg/mips: Create and use TCG_REG_TB, Richard Henderson, 2023/04/07
- [PATCH 06/12] tcg/mips: Split out tcg_out_movi_two, Richard Henderson, 2023/04/07