Re: [Patch 02/14] target/riscv: Fix the relationship between Zhinxmin and Zhinx

[Daniel Henrique Barboza]

On 2/14/23 05:38, Weiwei Li wrote:
> Just like zfh and zfhmin, Zhinxmin is part of Zhinx so Zhinxmin
> will be enabled when Zhinx is enabled
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.c | 7 +++++--
>   1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index eb0cd12a6a..9a89bea2a3 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -754,8 +754,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>       }
>   
>       /* Set the ISA extensions, checks should have happened above */
> -    if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
> -        cpu->cfg.ext_zhinxmin) {
> +    if (cpu->cfg.ext_zhinx) {
> +        cpu->cfg.ext_zhinxmin = true;
> +    }
> +
> +    if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) {
>           cpu->cfg.ext_zfinx = true;
>       }
>