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[PULL 04/32] target/riscv: Update VS timer whenever htimedelta changes
From: |
Alistair Francis |
Subject: |
[PULL 04/32] target/riscv: Update VS timer whenever htimedelta changes |
Date: |
Tue, 7 Feb 2023 17:09:15 +1000 |
From: Anup Patel <apatel@ventanamicro.com>
The htimedelta[h] CSR has impact on the VS timer comparison so we
should call riscv_timer_write_timecmp() whenever htimedelta changes.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 62e6c4acbd..fa17d7770c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3045,6 +3045,8 @@ static RISCVException read_htimedelta(CPURISCVState *env,
int csrno,
static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
target_ulong val)
{
+ RISCVCPU *cpu = env_archcpu(env);
+
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -3054,6 +3056,12 @@ static RISCVException write_htimedelta(CPURISCVState
*env, int csrno,
} else {
env->htimedelta = val;
}
+
+ if (cpu->cfg.ext_sstc && env->rdtime_fn) {
+ riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+ env->htimedelta, MIP_VSTIP);
+ }
+
return RISCV_EXCP_NONE;
}
@@ -3071,11 +3079,19 @@ static RISCVException read_htimedeltah(CPURISCVState
*env, int csrno,
static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
target_ulong val)
{
+ RISCVCPU *cpu = env_archcpu(env);
+
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
+
+ if (cpu->cfg.ext_sstc && env->rdtime_fn) {
+ riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+ env->htimedelta, MIP_VSTIP);
+ }
+
return RISCV_EXCP_NONE;
}
--
2.39.1
- [PULL 00/32] riscv-to-apply queue, Alistair Francis, 2023/02/07
- [PULL 02/32] include/hw/riscv/opentitan: update opentitan IRQs, Alistair Francis, 2023/02/07
- [PULL 03/32] hw/riscv: boot: Don't use CSRs if they are disabled, Alistair Francis, 2023/02/07
- [PULL 01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw, Alistair Francis, 2023/02/07
- [PULL 05/32] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP, Alistair Francis, 2023/02/07
- [PULL 06/32] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX, Alistair Francis, 2023/02/07
- [PULL 08/32] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic(), Alistair Francis, 2023/02/07
- [PULL 10/32] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms', Alistair Francis, 2023/02/07
- [PULL 04/32] target/riscv: Update VS timer whenever htimedelta changes,
Alistair Francis <=
- [PULL 11/32] target/riscv: set tval for triggered watchpoints, Alistair Francis, 2023/02/07
- [PULL 07/32] target/riscv: Ensure opcode is saved for all relevant instructions, Alistair Francis, 2023/02/07
- [PULL 12/32] hw/riscv/boot.c: calculate fdt size after fdt_pack(), Alistair Francis, 2023/02/07
- [PULL 09/32] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms', Alistair Francis, 2023/02/07
- [PULL 13/32] hw/riscv: split fdt address calculation from fdt load, Alistair Francis, 2023/02/07
- [PULL 14/32] hw/riscv: change riscv_compute_fdt_addr() semantics, Alistair Francis, 2023/02/07
- [PULL 16/32] RISC-V: Adding XTheadSync ISA extension, Alistair Francis, 2023/02/07
- [PULL 15/32] RISC-V: Adding XTheadCmo ISA extension, Alistair Francis, 2023/02/07
- [PULL 17/32] RISC-V: Adding XTheadBa ISA extension, Alistair Francis, 2023/02/07
- [PULL 18/32] RISC-V: Adding XTheadBb ISA extension, Alistair Francis, 2023/02/07