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[PULL 05/32] target/riscv: Don't clear mask in riscv_cpu_update_mip() fo
From: |
Alistair Francis |
Subject: |
[PULL 05/32] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP |
Date: |
Tue, 7 Feb 2023 17:09:16 +1000 |
From: Anup Patel <apatel@ventanamicro.com>
Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
for VSTIP.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 2 --
target/riscv/time_helper.c | 12 ++++++++----
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9a28816521..0d72466f3b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -621,8 +621,6 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask,
uint64_t value)
vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
}
- /* No need to update mip for VSTIP */
- mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask;
vstip = env->vstime_irq ? MIP_VSTIP : 0;
QEMU_IOTHREAD_LOCK_GUARD();
diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
index 8cce667dfd..4fb2a471a9 100644
--- a/target/riscv/time_helper.c
+++ b/target/riscv/time_helper.c
@@ -27,7 +27,7 @@ static void riscv_vstimer_cb(void *opaque)
RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
env->vstime_irq = 1;
- riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1));
+ riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
}
static void riscv_stimer_cb(void *opaque)
@@ -57,16 +57,20 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer
*timer,
*/
if (timer_irq == MIP_VSTIP) {
env->vstime_irq = 1;
+ riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
+ } else {
+ riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
}
- riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1));
return;
}
+ /* Clear the [VS|S]TIP bit in mip */
if (timer_irq == MIP_VSTIP) {
env->vstime_irq = 0;
+ riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0));
+ } else {
+ riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
}
- /* Clear the [V]STIP bit in mip */
- riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
/* otherwise, set up the future timer interrupt */
diff = timecmp - rtc_r;
--
2.39.1
- [PULL 00/32] riscv-to-apply queue, Alistair Francis, 2023/02/07
- [PULL 02/32] include/hw/riscv/opentitan: update opentitan IRQs, Alistair Francis, 2023/02/07
- [PULL 03/32] hw/riscv: boot: Don't use CSRs if they are disabled, Alistair Francis, 2023/02/07
- [PULL 01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw, Alistair Francis, 2023/02/07
- [PULL 05/32] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP,
Alistair Francis <=
- [PULL 06/32] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX, Alistair Francis, 2023/02/07
- [PULL 08/32] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic(), Alistair Francis, 2023/02/07
- [PULL 10/32] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms', Alistair Francis, 2023/02/07
- [PULL 04/32] target/riscv: Update VS timer whenever htimedelta changes, Alistair Francis, 2023/02/07
- [PULL 11/32] target/riscv: set tval for triggered watchpoints, Alistair Francis, 2023/02/07
- [PULL 07/32] target/riscv: Ensure opcode is saved for all relevant instructions, Alistair Francis, 2023/02/07
- [PULL 12/32] hw/riscv/boot.c: calculate fdt size after fdt_pack(), Alistair Francis, 2023/02/07
- [PULL 09/32] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms', Alistair Francis, 2023/02/07
- [PULL 13/32] hw/riscv: split fdt address calculation from fdt load, Alistair Francis, 2023/02/07
- [PULL 14/32] hw/riscv: change riscv_compute_fdt_addr() semantics, Alistair Francis, 2023/02/07