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[PULL 10/32] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'
From: |
Alistair Francis |
Subject: |
[PULL 10/32] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' |
Date: |
Tue, 7 Feb 2023 17:09:21 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Follow the QEMU convention of naming MachineState pointers as 'ms' by
renaming the instances where we're calling it 'mc'.
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230124212234.412630-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/spike.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index badc11ec43..04d236296b 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -56,7 +56,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry
*memmap,
uint64_t addr, size;
unsigned long clint_addr;
int cpu, socket;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
uint32_t *clint_cells;
uint32_t cpu_phandle, intc_phandle, phandle = 1;
char *name, *mem_name, *clint_name, *clust_name;
@@ -65,7 +65,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry
*memmap,
"sifive,clint0", "riscv,clint0"
};
- fdt = mc->fdt = create_device_tree(&fdt_size);
+ fdt = ms->fdt = create_device_tree(&fdt_size);
if (!fdt) {
error_report("create_device_tree() failed");
exit(1);
@@ -96,7 +96,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry
*memmap,
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
- for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+ for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) {
clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
qemu_fdt_add_subnode(fdt, clust_name);
@@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry
*memmap,
qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
s->soc[socket].hartid_base + cpu);
qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
- riscv_socket_fdt_write_id(mc, cpu_name, socket);
+ riscv_socket_fdt_write_id(ms, cpu_name, socket);
qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
@@ -147,14 +147,14 @@ static void create_fdt(SpikeState *s, const MemMapEntry
*memmap,
g_free(cpu_name);
}
- addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
- size = riscv_socket_mem_size(mc, socket);
+ addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket);
+ size = riscv_socket_mem_size(ms, socket);
mem_name = g_strdup_printf("/memory@%lx", (long)addr);
qemu_fdt_add_subnode(fdt, mem_name);
qemu_fdt_setprop_cells(fdt, mem_name, "reg",
addr >> 32, addr, size >> 32, size);
qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
- riscv_socket_fdt_write_id(mc, mem_name, socket);
+ riscv_socket_fdt_write_id(ms, mem_name, socket);
g_free(mem_name);
clint_addr = memmap[SPIKE_CLINT].base +
@@ -167,14 +167,14 @@ static void create_fdt(SpikeState *s, const MemMapEntry
*memmap,
0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
- riscv_socket_fdt_write_id(mc, clint_name, socket);
+ riscv_socket_fdt_write_id(ms, clint_name, socket);
g_free(clint_name);
g_free(clint_cells);
g_free(clust_name);
}
- riscv_socket_fdt_write_distance_matrix(mc);
+ riscv_socket_fdt_write_distance_matrix(ms);
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
--
2.39.1
- [PULL 00/32] riscv-to-apply queue, Alistair Francis, 2023/02/07
- [PULL 02/32] include/hw/riscv/opentitan: update opentitan IRQs, Alistair Francis, 2023/02/07
- [PULL 03/32] hw/riscv: boot: Don't use CSRs if they are disabled, Alistair Francis, 2023/02/07
- [PULL 01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw, Alistair Francis, 2023/02/07
- [PULL 05/32] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP, Alistair Francis, 2023/02/07
- [PULL 06/32] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX, Alistair Francis, 2023/02/07
- [PULL 08/32] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic(), Alistair Francis, 2023/02/07
- [PULL 10/32] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms',
Alistair Francis <=
- [PULL 04/32] target/riscv: Update VS timer whenever htimedelta changes, Alistair Francis, 2023/02/07
- [PULL 11/32] target/riscv: set tval for triggered watchpoints, Alistair Francis, 2023/02/07
- [PULL 07/32] target/riscv: Ensure opcode is saved for all relevant instructions, Alistair Francis, 2023/02/07
- [PULL 12/32] hw/riscv/boot.c: calculate fdt size after fdt_pack(), Alistair Francis, 2023/02/07
- [PULL 09/32] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms', Alistair Francis, 2023/02/07
- [PULL 13/32] hw/riscv: split fdt address calculation from fdt load, Alistair Francis, 2023/02/07
- [PULL 14/32] hw/riscv: change riscv_compute_fdt_addr() semantics, Alistair Francis, 2023/02/07
- [PULL 16/32] RISC-V: Adding XTheadSync ISA extension, Alistair Francis, 2023/02/07
- [PULL 15/32] RISC-V: Adding XTheadCmo ISA extension, Alistair Francis, 2023/02/07
- [PULL 17/32] RISC-V: Adding XTheadBa ISA extension, Alistair Francis, 2023/02/07