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[PULL 0/5] target-arm queue
From: |
Peter Maydell |
Subject: |
[PULL 0/5] target-arm queue |
Date: |
Mon, 21 Nov 2022 13:02:34 +0000 |
Hi; here's a collection of Arm bug fixes for rc2.
thanks
-- PMM
The following changes since commit a082fab9d259473a9d5d53307cf83b1223301181:
Merge tag 'pull-ppc-20221117' of https://gitlab.com/danielhb/qemu into
staging (2022-11-17 12:39:38 -0500)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20221121
for you to fetch changes up to 312b71abce3005ca7294dc0db7d548dc7cc41fbf:
target/arm: Limit LPA2 effective output address when TCR.DS == 0 (2022-11-21
11:46:46 +0000)
----------------------------------------------------------------
target-arm queue:
* hw/sd: Fix sun4i allwinner-sdhost for U-Boot
* hw/intc: add implementation of GICD_IIDR to Arm GIC
* tests/avocado/boot_linux.py: Bump aarch64 virt test timeout
* target/arm: Limit LPA2 effective output address when TCR.DS == 0
----------------------------------------------------------------
Alex Bennée (2):
hw/intc: clean-up access to GIC multi-byte registers
hw/intc: add implementation of GICD_IIDR to Arm GIC
Ard Biesheuvel (1):
target/arm: Limit LPA2 effective output address when TCR.DS == 0
Peter Maydell (1):
tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s
Strahinja Jankovic (1):
hw/sd: Fix sun4i allwinner-sdhost for U-Boot
include/hw/sd/allwinner-sdhost.h | 1 +
hw/intc/arm_gic.c | 28 ++++++++++++-----
hw/sd/allwinner-sdhost.c | 67 +++++++++++++++++++++++++++-------------
target/arm/ptw.c | 8 +++++
tests/avocado/boot_linux.py | 2 +-
5 files changed, 77 insertions(+), 29 deletions(-)
- [PULL 0/5] target-arm queue,
Peter Maydell <=
- [PULL 3/5] hw/intc: add implementation of GICD_IIDR to Arm GIC, Peter Maydell, 2022/11/21
- [PULL 4/5] tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s, Peter Maydell, 2022/11/21
- [PULL 1/5] hw/sd: Fix sun4i allwinner-sdhost for U-Boot, Peter Maydell, 2022/11/21
- [PULL 2/5] hw/intc: clean-up access to GIC multi-byte registers, Peter Maydell, 2022/11/21
- [PULL 5/5] target/arm: Limit LPA2 effective output address when TCR.DS == 0, Peter Maydell, 2022/11/21
- Re: [PULL 0/5] target-arm queue, Stefan Hajnoczi, 2022/11/21