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[PATCH for-8.0 25/29] tcg/i386: Mark Win64 call-saved vector regs as res
From: |
Richard Henderson |
Subject: |
[PATCH for-8.0 25/29] tcg/i386: Mark Win64 call-saved vector regs as reserved |
Date: |
Fri, 18 Nov 2022 01:47:50 -0800 |
While we do not include these in tcg_target_reg_alloc_order,
and therefore they ought never be allocated, it seems safer
to mark them reserved as well.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index e38f08bd12..e04818eef6 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -4224,6 +4224,19 @@ static void tcg_target_init(TCGContext *s)
s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
+#ifdef _WIN64
+ /* These are call saved, and not we don't save them, so don't use them. */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM6);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM7);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM8);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM9);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM10);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM11);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM12);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM13);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM14);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM15);
+#endif
}
typedef struct {
--
2.34.1
- [PATCH for-8.0 21/29] tcg/i386: Introduce tcg_out_mov2, (continued)
- [PATCH for-8.0 21/29] tcg/i386: Introduce tcg_out_mov2, Richard Henderson, 2022/11/18
- [PATCH for-8.0 24/29] tcg/i386: Replace is64 with type in qemu_ld/st routines, Richard Henderson, 2022/11/18
- [PATCH for-8.0 28/29] tcg/i386: Add vex_v argument to tcg_out_vex_modrm_pool, Richard Henderson, 2022/11/18
- [PATCH for-8.0 27/29] tcg/i386: Support 128-bit load/store with have_atomic16, Richard Henderson, 2022/11/18
- [PATCH for-8.0 17/29] tcg/aarch64: Add have_lse, have_lse2, Richard Henderson, 2022/11/18
- [PATCH for-8.0 18/29] accel/tcg: Add aarch64 specific support in ldst_atomicity, Richard Henderson, 2022/11/18
- [PATCH for-8.0 25/29] tcg/i386: Mark Win64 call-saved vector regs as reserved,
Richard Henderson <=
- [PATCH for-8.0 29/29] tcg/i386: Honor 64-bit atomicity in 32-bit mode, Richard Henderson, 2022/11/18
- [PATCH for-8.0 19/29] tcg: Introduce TCG_OPF_TYPE_MASK, Richard Henderson, 2022/11/18
- [PATCH for-8.0 20/29] tcg: Add INDEX_op_qemu_{ld,st}_i128, Richard Henderson, 2022/11/18
- [PATCH for-8.0 16/29] accel/tcg: Use have_atomic16 in ldst_atomicity.c.inc, Richard Henderson, 2022/11/18
- [PATCH for-8.0 13/29] meson: Detect atomic128 support with optimization, Richard Henderson, 2022/11/18
- [PATCH for-8.0 15/29] include/qemu/int128: Add vector type to Int128Alias, Richard Henderson, 2022/11/18