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[PATCH for-8.0 21/29] tcg/i386: Introduce tcg_out_mov2
From: |
Richard Henderson |
Subject: |
[PATCH for-8.0 21/29] tcg/i386: Introduce tcg_out_mov2 |
Date: |
Fri, 18 Nov 2022 01:47:46 -0800 |
Create a helper for data movement minding register overlap.
Use the more general xchg instruction, which consumes one
extra byte, but simplifies the more general function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 27 +++++++++++++++++++++------
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index f4c0c7b8a2..79568a3981 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -461,6 +461,7 @@ static bool tcg_target_const_match(int64_t val, TCGType
type, int ct)
#define OPC_VPTERNLOGQ (0x25 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VZEROUPPER (0x77 | P_EXT)
#define OPC_XCHG_ax_r32 (0x90)
+#define OPC_XCHG_EvGv (0x87)
#define OPC_GRP3_Eb (0xf6)
#define OPC_GRP3_Ev (0xf7)
@@ -1880,6 +1881,24 @@ static void add_qemu_ldst_label(TCGContext *s, bool
is_ld, bool is_64,
}
}
+/* Move src1 to dst1 and src2 to dst2, minding possible overlap. */
+static void tcg_out_mov2(TCGContext *s,
+ TCGType type1, TCGReg dst1, TCGReg src1,
+ TCGType type2, TCGReg dst2, TCGReg src2)
+{
+ if (dst1 != src2) {
+ tcg_out_mov(s, type1, dst1, src1);
+ tcg_out_mov(s, type2, dst2, src2);
+ } else if (dst2 != src1) {
+ tcg_out_mov(s, type2, dst2, src2);
+ tcg_out_mov(s, type1, dst1, src1);
+ } else {
+ /* dst1 == src2 && dst2 == src1 -> xchg. */
+ int w = (type1 == TCG_TYPE_I32 && type2 == TCG_TYPE_I32 ? 0 : P_REXW);
+ tcg_out_modrm(s, OPC_XCHG_EvGv + w, dst1, dst2);
+ }
+}
+
/*
* Generate code for the slow path for a load at the end of block
*/
@@ -1947,13 +1966,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,
TCGLabelQemuLdst *l)
case MO_UQ:
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX);
- } else if (data_reg == TCG_REG_EDX) {
- /* xchg %edx, %eax */
- tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0);
- tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EAX);
} else {
- tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);
- tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX);
+ tcg_out_mov2(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX,
+ TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX);
}
break;
default:
--
2.34.1
- [PATCH for-8.0 06/29] accel/tcg: Reorg system mode store helpers, (continued)
- [PATCH for-8.0 06/29] accel/tcg: Reorg system mode store helpers, Richard Henderson, 2022/11/18
- [PATCH for-8.0 07/29] accel/tcg: Honor atomicity of loads, Richard Henderson, 2022/11/18
- [PATCH for-8.0 09/29] tcg/tci: Use cpu_{ld,st}_mmu, Richard Henderson, 2022/11/18
- [PATCH for-8.0 08/29] accel/tcg: Honor atomicity of stores, Richard Henderson, 2022/11/18
- [PATCH for-8.0 11/29] accel/tcg: Implement helper_{ld, st}*_mmu for user-only, Richard Henderson, 2022/11/18
- [PATCH for-8.0 10/29] tcg: Unify helper_{be,le}_{ld,st}*, Richard Henderson, 2022/11/18
- [PATCH for-8.0 12/29] tcg: Add 128-bit guest memory primitives, Richard Henderson, 2022/11/18
- [PATCH for-8.0 21/29] tcg/i386: Introduce tcg_out_mov2,
Richard Henderson <=
- [PATCH for-8.0 24/29] tcg/i386: Replace is64 with type in qemu_ld/st routines, Richard Henderson, 2022/11/18
- [PATCH for-8.0 28/29] tcg/i386: Add vex_v argument to tcg_out_vex_modrm_pool, Richard Henderson, 2022/11/18
- [PATCH for-8.0 27/29] tcg/i386: Support 128-bit load/store with have_atomic16, Richard Henderson, 2022/11/18
- [PATCH for-8.0 17/29] tcg/aarch64: Add have_lse, have_lse2, Richard Henderson, 2022/11/18
- [PATCH for-8.0 18/29] accel/tcg: Add aarch64 specific support in ldst_atomicity, Richard Henderson, 2022/11/18
- [PATCH for-8.0 25/29] tcg/i386: Mark Win64 call-saved vector regs as reserved, Richard Henderson, 2022/11/18