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[PATCH for-8.0 28/29] tcg/i386: Add vex_v argument to tcg_out_vex_modrm_
From: |
Richard Henderson |
Subject: |
[PATCH for-8.0 28/29] tcg/i386: Add vex_v argument to tcg_out_vex_modrm_pool |
Date: |
Fri, 18 Nov 2022 01:47:53 -0800 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index f277085321..3f0cb4bc66 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -841,9 +841,9 @@ static inline void tcg_out_modrm_pool(TCGContext *s, int
opc, int r)
}
/* Output an opcode with an expected reference to the constant pool. */
-static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r)
+static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r, int v)
{
- tcg_out_vex_opc(s, opc, r, 0, 0, 0);
+ tcg_out_vex_opc(s, opc, r, v, 0, 0);
/* Absolute for 32-bit, pc-relative for 64-bit. */
tcg_out8(s, LOWREGMASK(r) << 3 | 5);
tcg_out32(s, 0);
@@ -990,18 +990,18 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
unsigned vece,
if (TCG_TARGET_REG_BITS == 32 && vece < MO_64) {
if (have_avx2) {
- tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret);
+ tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret, 0);
} else {
- tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret);
+ tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret, 0);
}
new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0);
} else {
if (type == TCG_TYPE_V64) {
- tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret);
+ tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret, 0);
} else if (have_avx2) {
- tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret);
+ tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret, 0);
} else {
- tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret);
+ tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret, 0);
}
if (TCG_TARGET_REG_BITS == 64) {
new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
@@ -1024,7 +1024,7 @@ static void tcg_out_movi_vec(TCGContext *s, TCGType type,
}
int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW);
- tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy + rexw, ret);
+ tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy + rexw, ret, 0);
if (TCG_TARGET_REG_BITS == 64) {
new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
} else {
--
2.34.1
- Re: [PATCH for-8.0 09/29] tcg/tci: Use cpu_{ld,st}_mmu, (continued)
- [PATCH for-8.0 08/29] accel/tcg: Honor atomicity of stores, Richard Henderson, 2022/11/18
- [PATCH for-8.0 11/29] accel/tcg: Implement helper_{ld, st}*_mmu for user-only, Richard Henderson, 2022/11/18
- [PATCH for-8.0 10/29] tcg: Unify helper_{be,le}_{ld,st}*, Richard Henderson, 2022/11/18
- [PATCH for-8.0 12/29] tcg: Add 128-bit guest memory primitives, Richard Henderson, 2022/11/18
- [PATCH for-8.0 21/29] tcg/i386: Introduce tcg_out_mov2, Richard Henderson, 2022/11/18
- [PATCH for-8.0 24/29] tcg/i386: Replace is64 with type in qemu_ld/st routines, Richard Henderson, 2022/11/18
- [PATCH for-8.0 28/29] tcg/i386: Add vex_v argument to tcg_out_vex_modrm_pool,
Richard Henderson <=
- [PATCH for-8.0 27/29] tcg/i386: Support 128-bit load/store with have_atomic16, Richard Henderson, 2022/11/18
- [PATCH for-8.0 17/29] tcg/aarch64: Add have_lse, have_lse2, Richard Henderson, 2022/11/18
- [PATCH for-8.0 18/29] accel/tcg: Add aarch64 specific support in ldst_atomicity, Richard Henderson, 2022/11/18
- [PATCH for-8.0 25/29] tcg/i386: Mark Win64 call-saved vector regs as reserved, Richard Henderson, 2022/11/18
- [PATCH for-8.0 29/29] tcg/i386: Honor 64-bit atomicity in 32-bit mode, Richard Henderson, 2022/11/18
- [PATCH for-8.0 19/29] tcg: Introduce TCG_OPF_TYPE_MASK, Richard Henderson, 2022/11/18