[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 48/54] hw/acpi/viot: build array of PCI host bridges before genera
From: |
Michael S. Tsirkin |
Subject: |
[PULL 48/54] hw/acpi/viot: build array of PCI host bridges before generating VIOT ACPI table |
Date: |
Fri, 10 Jun 2022 03:59:25 -0400 |
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Perform the generation of the VIOT ACPI table in 2 separate passes: the first
pass
enumerates all of the PCI host bridges and adds the min_bus and max_bus
information
to an array.
Once this is done the VIOT table header is generated using the size of the array
to calculate the node count, which means it is no longer necessary to use a
sub-array to hold the PCI host bridge range information along with viommu_off.
Finally the PCI host bridge array is iterated again to add the required entries
to the final VIOT ACPI table.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220525173232.31429-4-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/viot.c | 42 ++++++++++++++++++++++++------------------
1 file changed, 24 insertions(+), 18 deletions(-)
diff --git a/hw/acpi/viot.c b/hw/acpi/viot.c
index 5dafcbf5ef..c32bbdd180 100644
--- a/hw/acpi/viot.c
+++ b/hw/acpi/viot.c
@@ -10,10 +10,9 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
-struct viot_pci_ranges {
- GArray *blob;
- size_t count;
- uint16_t output_node;
+struct viot_pci_host_range {
+ int min_bus;
+ int max_bus;
};
static void build_pci_host_range(GArray *table_data, int min_bus, int max_bus,
@@ -44,8 +43,7 @@ static void build_pci_host_range(GArray *table_data, int
min_bus, int max_bus,
/* Build PCI range for a given PCI host bridge */
static int enumerate_pci_host_bridges(Object *obj, void *opaque)
{
- struct viot_pci_ranges *pci_ranges = opaque;
- GArray *blob = pci_ranges->blob;
+ GArray *pci_host_ranges = opaque;
if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
@@ -55,9 +53,11 @@ static int enumerate_pci_host_bridges(Object *obj, void
*opaque)
pci_bus_range(bus, &min_bus, &max_bus);
- build_pci_host_range(blob, min_bus, max_bus,
- pci_ranges->output_node);
- pci_ranges->count++;
+ const struct viot_pci_host_range pci_host_range = {
+ .min_bus = min_bus,
+ .max_bus = max_bus,
+ };
+ g_array_append_val(pci_host_ranges, pci_host_range);
}
}
@@ -78,19 +78,19 @@ void build_viot(MachineState *ms, GArray *table_data,
BIOSLinker *linker,
int viommu_off = 48;
AcpiTable table = { .sig = "VIOT", .rev = 0,
.oem_id = oem_id, .oem_table_id = oem_table_id };
- struct viot_pci_ranges pci_ranges = {
- .output_node = viommu_off,
- .blob = g_array_new(false, true /* clear */, 1),
- };
+ GArray *pci_host_ranges = g_array_new(false, true,
+ sizeof(struct viot_pci_host_range));
+ struct viot_pci_host_range *pci_host_range;
+ int i;
/* Build the list of PCI ranges that this viommu manages */
object_child_foreach_recursive(OBJECT(ms), enumerate_pci_host_bridges,
- &pci_ranges);
+ pci_host_ranges);
/* ACPI table header */
acpi_table_begin(&table, table_data);
/* Node count */
- build_append_int_noprefix(table_data, pci_ranges.count + 1, 2);
+ build_append_int_noprefix(table_data, pci_host_ranges->len + 1, 2);
/* Node offset */
build_append_int_noprefix(table_data, viommu_off, 2);
/* Reserved */
@@ -111,9 +111,15 @@ void build_viot(MachineState *ms, GArray *table_data,
BIOSLinker *linker,
build_append_int_noprefix(table_data, 0, 8);
/* PCI ranges found above */
- g_array_append_vals(table_data, pci_ranges.blob->data,
- pci_ranges.blob->len);
- g_array_free(pci_ranges.blob, true);
+ for (i = 0; i < pci_host_ranges->len; i++) {
+ pci_host_range = &g_array_index(pci_host_ranges,
+ struct viot_pci_host_range, i);
+
+ build_pci_host_range(table_data, pci_host_range->min_bus,
+ pci_host_range->max_bus, viommu_off);
+ }
+
+ g_array_free(pci_host_ranges, true);
acpi_table_end(linker, &table);
}
--
MST
- [PULL 40/54] pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup., (continued)
- [PULL 40/54] pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup., Michael S. Tsirkin, 2022/06/10
- [PULL 35/54] x86: acpi-build: do not include hw/isa/isa.h directly, Michael S. Tsirkin, 2022/06/10
- [PULL 43/54] hw/machine: Drop cxl_supported flag as no longer useful, Michael S. Tsirkin, 2022/06/10
- [PULL 42/54] hw/cxl: Move the CXLState from MachineState to machine type specific state., Michael S. Tsirkin, 2022/06/10
- [PULL 36/54] hw/cxl: Make the CXL fixed memory window setup a machine parameter., Michael S. Tsirkin, 2022/06/10
- [PULL 41/54] tests/acpi: Update q35/CEDT.cxl for new memory addresses., Michael S. Tsirkin, 2022/06/10
- [PULL 44/54] pci: fix overflow in snprintf string formatting, Michael S. Tsirkin, 2022/06/10
- [PULL 45/54] hw/cxl: Fix missing write mask for HDM decoder target list registers, Michael S. Tsirkin, 2022/06/10
- [PULL 46/54] hw/acpi/viot: rename build_pci_range_node() to enumerate_pci_host_bridges(), Michael S. Tsirkin, 2022/06/10
- [PULL 47/54] hw/acpi/viot: move the individual PCI host bridge entry generation to a new function, Michael S. Tsirkin, 2022/06/10
- [PULL 48/54] hw/acpi/viot: build array of PCI host bridges before generating VIOT ACPI table,
Michael S. Tsirkin <=
- [PULL 49/54] tests/acpi: virt: allow VIOT acpi table changes, Michael S. Tsirkin, 2022/06/10
- [PULL 50/54] hw/acpi/viot: sort VIOT ACPI table entries by PCI host bridge min_bus, Michael S. Tsirkin, 2022/06/10
- [PULL 51/54] tests/acpi: virt: update golden masters for VIOT, Michael S. Tsirkin, 2022/06/10
- [PULL 52/54] hw/virtio/vhost-user: don't use uninitialized variable, Michael S. Tsirkin, 2022/06/10
- [PULL 53/54] hw/vhost-user-scsi|blk: set `supports_config` flag correctly, Michael S. Tsirkin, 2022/06/10
- [PULL 54/54] crypto: Introduce RSA algorithm, Michael S. Tsirkin, 2022/06/10