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[PULL 46/54] hw/acpi/viot: rename build_pci_range_node() to enumerate_pc
From: |
Michael S. Tsirkin |
Subject: |
[PULL 46/54] hw/acpi/viot: rename build_pci_range_node() to enumerate_pci_host_bridges() |
Date: |
Fri, 10 Jun 2022 03:59:19 -0400 |
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This is in preparation for separating out the VIOT ACPI table build from the
PCI host bridge numeration.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220525173232.31429-2-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/viot.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/acpi/viot.c b/hw/acpi/viot.c
index c1af75206e..a41daded71 100644
--- a/hw/acpi/viot.c
+++ b/hw/acpi/viot.c
@@ -17,7 +17,7 @@ struct viot_pci_ranges {
};
/* Build PCI range for a given PCI host bridge */
-static int build_pci_range_node(Object *obj, void *opaque)
+static int enumerate_pci_host_bridges(Object *obj, void *opaque)
{
struct viot_pci_ranges *pci_ranges = opaque;
GArray *blob = pci_ranges->blob;
@@ -78,7 +78,7 @@ void build_viot(MachineState *ms, GArray *table_data,
BIOSLinker *linker,
};
/* Build the list of PCI ranges that this viommu manages */
- object_child_foreach_recursive(OBJECT(ms), build_pci_range_node,
+ object_child_foreach_recursive(OBJECT(ms), enumerate_pci_host_bridges,
&pci_ranges);
/* ACPI table header */
--
MST
- [PULL 39/54] tests/acpi: Allow modification of q35 CXL CEDT table., (continued)
- [PULL 39/54] tests/acpi: Allow modification of q35 CXL CEDT table., Michael S. Tsirkin, 2022/06/10
- [PULL 37/54] hw/acpi/cxl: Pass in the CXLState directly rather than MachineState, Michael S. Tsirkin, 2022/06/10
- [PULL 40/54] pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup., Michael S. Tsirkin, 2022/06/10
- [PULL 35/54] x86: acpi-build: do not include hw/isa/isa.h directly, Michael S. Tsirkin, 2022/06/10
- [PULL 43/54] hw/machine: Drop cxl_supported flag as no longer useful, Michael S. Tsirkin, 2022/06/10
- [PULL 42/54] hw/cxl: Move the CXLState from MachineState to machine type specific state., Michael S. Tsirkin, 2022/06/10
- [PULL 36/54] hw/cxl: Make the CXL fixed memory window setup a machine parameter., Michael S. Tsirkin, 2022/06/10
- [PULL 41/54] tests/acpi: Update q35/CEDT.cxl for new memory addresses., Michael S. Tsirkin, 2022/06/10
- [PULL 44/54] pci: fix overflow in snprintf string formatting, Michael S. Tsirkin, 2022/06/10
- [PULL 45/54] hw/cxl: Fix missing write mask for HDM decoder target list registers, Michael S. Tsirkin, 2022/06/10
- [PULL 46/54] hw/acpi/viot: rename build_pci_range_node() to enumerate_pci_host_bridges(),
Michael S. Tsirkin <=
- [PULL 47/54] hw/acpi/viot: move the individual PCI host bridge entry generation to a new function, Michael S. Tsirkin, 2022/06/10
- [PULL 48/54] hw/acpi/viot: build array of PCI host bridges before generating VIOT ACPI table, Michael S. Tsirkin, 2022/06/10
- [PULL 49/54] tests/acpi: virt: allow VIOT acpi table changes, Michael S. Tsirkin, 2022/06/10
- [PULL 50/54] hw/acpi/viot: sort VIOT ACPI table entries by PCI host bridge min_bus, Michael S. Tsirkin, 2022/06/10
- [PULL 51/54] tests/acpi: virt: update golden masters for VIOT, Michael S. Tsirkin, 2022/06/10
- [PULL 52/54] hw/virtio/vhost-user: don't use uninitialized variable, Michael S. Tsirkin, 2022/06/10
- [PULL 53/54] hw/vhost-user-scsi|blk: set `supports_config` flag correctly, Michael S. Tsirkin, 2022/06/10
- [PULL 54/54] crypto: Introduce RSA algorithm, Michael S. Tsirkin, 2022/06/10