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[PULL 40/54] pci/pci_expander_bridge: For CXL HB delay the HB register m
From: |
Michael S. Tsirkin |
Subject: |
[PULL 40/54] pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup. |
Date: |
Fri, 10 Jun 2022 03:59:00 -0400 |
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
As the CXLState will no long be accessible via MachineState
at time of PXB_CXL realization, come back later from the machine specific
code to fill in the missing memory region setup. Only at this stage
is it possible to check if cxl=on, so that check is moved to this
later point.
Note that for multiple host bridges, the allocation order of the
register spaces is changed. This will be reflected in ACPI CEDT.
Stubs are added to handle case of CONFIG_PXB=n for machines that
call these functions.
The bus walking logic is common to all machines so add a utility
function + stub to cxl-host*.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Message-Id: <20220608145440.26106-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/cxl/cxl_host.h | 1 +
include/hw/pci-bridge/pci_expander_bridge.h | 12 ++++++++
hw/cxl/cxl-host-stubs.c | 1 +
hw/cxl/cxl-host.c | 20 +++++++++++++
hw/i386/pc.c | 3 ++
hw/pci-bridge/pci_expander_bridge.c | 32 +++++++++++++--------
hw/pci-bridge/pci_expander_bridge_stubs.c | 14 +++++++++
hw/pci-bridge/meson.build | 5 +++-
8 files changed, 75 insertions(+), 13 deletions(-)
create mode 100644 include/hw/pci-bridge/pci_expander_bridge.h
create mode 100644 hw/pci-bridge/pci_expander_bridge_stubs.c
diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h
index 4d642a81fa..a1b662ce40 100644
--- a/include/hw/cxl/cxl_host.h
+++ b/include/hw/cxl/cxl_host.h
@@ -16,6 +16,7 @@
void cxl_machine_init(Object *obj, CXLState *state);
void cxl_fmws_link_targets(CXLState *stat, Error **errp);
+void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp);
extern const MemoryRegionOps cfmws_ops;
diff --git a/include/hw/pci-bridge/pci_expander_bridge.h
b/include/hw/pci-bridge/pci_expander_bridge.h
new file mode 100644
index 0000000000..0b3856d615
--- /dev/null
+++ b/include/hw/pci-bridge/pci_expander_bridge.h
@@ -0,0 +1,12 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef PCI_EXPANDER_BRIDGE_H
+#define PCI_EXPANDER_BRIDGE_H
+
+#include "hw/cxl/cxl.h"
+
+void pxb_cxl_hook_up_registers(CXLState *state, PCIBus *bus, Error **errp);
+
+#endif /* PCI_EXPANDER_BRIDGE_H */
diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c
index e0d5ec8ad5..cae4afcdde 100644
--- a/hw/cxl/cxl-host-stubs.c
+++ b/hw/cxl/cxl-host-stubs.c
@@ -10,5 +10,6 @@
void cxl_fmws_link_targets(CXLState *stat, Error **errp) {};
void cxl_machine_init(Object *obj, CXLState *state) {};
+void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp) {};
const MemoryRegionOps cfmws_ops;
diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
index 8e7738a65b..efa14908d8 100644
--- a/hw/cxl/cxl-host.c
+++ b/hw/cxl/cxl-host.c
@@ -20,6 +20,7 @@
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_host.h"
#include "hw/pci/pcie_port.h"
+#include "hw/pci-bridge/pci_expander_bridge.h"
static void cxl_fixed_memory_window_config(CXLState *cxl_state,
CXLFixedMemoryWindowOptions *object,
@@ -280,3 +281,22 @@ void cxl_machine_init(Object *obj, CXLState *state)
object_property_set_description(obj, "cxl-fmw",
"CXL Fixed Memory Windows (array)");
}
+
+void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp)
+{
+ /* Walk the pci busses looking for pxb busses to hook up */
+ if (bus) {
+ QLIST_FOREACH(bus, &bus->child, sibling) {
+ if (!pci_bus_is_root(bus)) {
+ continue;
+ }
+ if (pci_bus_is_cxl(bus)) {
+ if (!state->is_enabled) {
+ error_setg(errp, "CXL host bridges present, but cxl=off");
+ return;
+ }
+ pxb_cxl_hook_up_registers(state, bus, errp);
+ }
+ }
+ }
+}
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 6cecd74d58..9f48d02739 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -37,6 +37,7 @@
#include "hw/ide.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
+#include "hw/pci-bridge/pci_expander_bridge.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/timer/hpet.h"
#include "hw/firmware/smbios.h"
@@ -735,6 +736,8 @@ void pc_machine_done(Notifier *notifier, void *data)
MachineState *ms = MACHINE(pcms);
if (ms->cxl_devices_state) {
+ cxl_hook_up_pxb_registers(pcms->bus, ms->cxl_devices_state,
+ &error_fatal);
cxl_fmws_link_targets(ms->cxl_devices_state, &error_fatal);
}
diff --git a/hw/pci-bridge/pci_expander_bridge.c
b/hw/pci-bridge/pci_expander_bridge.c
index 02032360f5..c9e817aa58 100644
--- a/hw/pci-bridge/pci_expander_bridge.c
+++ b/hw/pci-bridge/pci_expander_bridge.c
@@ -17,6 +17,7 @@
#include "hw/pci/pci_host.h"
#include "hw/qdev-properties.h"
#include "hw/pci/pci_bridge.h"
+#include "hw/pci-bridge/pci_expander_bridge.h"
#include "hw/cxl/cxl.h"
#include "qemu/range.h"
#include "qemu/error-report.h"
@@ -186,25 +187,38 @@ static const TypeInfo pxb_host_info = {
static void pxb_cxl_realize(DeviceState *dev, Error **errp)
{
- MachineState *ms = MACHINE(qdev_get_machine());
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
CXLHost *cxl = PXB_CXL_HOST(dev);
CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
struct MemoryRegion *mr = &cxl_cstate->crb.component_registers;
- hwaddr offset;
cxl_component_register_block_init(OBJECT(dev), cxl_cstate,
TYPE_PXB_CXL_HOST);
sysbus_init_mmio(sbd, mr);
+}
- offset = memory_region_size(mr) * ms->cxl_devices_state->next_mr_idx;
- if (offset > memory_region_size(&ms->cxl_devices_state->host_mr)) {
+/*
+ * Host bridge realization has no means of knowning state associated
+ * with a particular machine. As such, it is nececssary to delay
+ * final setup of the host bridge register space until later in the
+ * machine bring up.
+ */
+void pxb_cxl_hook_up_registers(CXLState *cxl_state, PCIBus *bus, Error **errp)
+{
+ PXBDev *pxb = PXB_CXL_DEV(pci_bridge_get_device(bus));
+ CXLHost *cxl = pxb->cxl.cxl_host_bridge;
+ CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
+ struct MemoryRegion *mr = &cxl_cstate->crb.component_registers;
+ hwaddr offset;
+
+ offset = memory_region_size(mr) * cxl_state->next_mr_idx;
+ if (offset > memory_region_size(&cxl_state->host_mr)) {
error_setg(errp, "Insufficient space for pxb cxl host register space");
return;
}
- memory_region_add_subregion(&ms->cxl_devices_state->host_mr, offset, mr);
- ms->cxl_devices_state->next_mr_idx++;
+ memory_region_add_subregion(&cxl_state->host_mr, offset, mr);
+ cxl_state->next_mr_idx++;
}
static void pxb_cxl_host_class_init(ObjectClass *class, void *data)
@@ -461,17 +475,11 @@ static const TypeInfo pxb_pcie_dev_info = {
static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp)
{
- MachineState *ms = MACHINE(qdev_get_machine());
-
/* A CXL PXB's parent bus is still PCIe */
if (!pci_bus_is_express(pci_get_bus(dev))) {
error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus");
return;
}
- if (!ms->cxl_devices_state || !ms->cxl_devices_state->is_enabled) {
- error_setg(errp, "Machine does not have cxl=on");
- return;
- }
pxb_dev_realize_common(dev, CXL, errp);
pxb_dev_reset(DEVICE(dev));
diff --git a/hw/pci-bridge/pci_expander_bridge_stubs.c
b/hw/pci-bridge/pci_expander_bridge_stubs.c
new file mode 100644
index 0000000000..b35180311f
--- /dev/null
+++ b/hw/pci-bridge/pci_expander_bridge_stubs.c
@@ -0,0 +1,14 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Stubs for calls made from machines to handle the case where CONFIG_PXB
+ * is not enabled.
+ */
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/pci-bridge/pci_expander_bridge.h"
+#include "hw/cxl/cxl.h"
+
+void pxb_cxl_hook_up_registers(CXLState *state, PCIBus *bus, Error **errp) {};
diff --git a/hw/pci-bridge/meson.build b/hw/pci-bridge/meson.build
index b6d26a03d5..fdbe2e07c5 100644
--- a/hw/pci-bridge/meson.build
+++ b/hw/pci-bridge/meson.build
@@ -3,7 +3,8 @@ pci_ss.add(files('pci_bridge_dev.c'))
pci_ss.add(when: 'CONFIG_I82801B11', if_true: files('i82801b11.c'))
pci_ss.add(when: 'CONFIG_IOH3420', if_true: files('ioh3420.c'))
pci_ss.add(when: 'CONFIG_PCIE_PORT', if_true: files('pcie_root_port.c',
'gen_pcie_root_port.c', 'pcie_pci_bridge.c'))
-pci_ss.add(when: 'CONFIG_PXB', if_true: files('pci_expander_bridge.c'))
+pci_ss.add(when: 'CONFIG_PXB', if_true: files('pci_expander_bridge.c'),
+ if_false: files('pci_expander_bridge_stubs.c'))
pci_ss.add(when: 'CONFIG_XIO3130', if_true: files('xio3130_upstream.c',
'xio3130_downstream.c'))
pci_ss.add(when: 'CONFIG_CXL', if_true: files('cxl_root_port.c'))
@@ -13,3 +14,5 @@ pci_ss.add(when: 'CONFIG_DEC_PCI', if_true: files('dec.c'))
pci_ss.add(when: 'CONFIG_SIMBA', if_true: files('simba.c'))
softmmu_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss)
+
+softmmu_ss.add(when: 'CONFIG_ALL', if_true:
files('pci_expander_bridge_stubs.c'))
--
MST
- [PULL 28/54] acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML, (continued)
- [PULL 28/54] acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML, Michael S. Tsirkin, 2022/06/10
- [PULL 29/54] tests: acpi: update expected DSDT.pvpanic-isa blob, Michael S. Tsirkin, 2022/06/10
- [PULL 30/54] tests: acpi: white-list DSDT.tis.tpm2/DSDT.tis.tpm12 expected blobs, Michael S. Tsirkin, 2022/06/10
- [PULL 34/54] tests: acpi: update expected DSDT.tis.tpm2/DSDT.tis.tpm12 blobs, Michael S. Tsirkin, 2022/06/10
- [PULL 32/54] acpi: pc/q35: remove not needed 'if' condition on pci bus, Michael S. Tsirkin, 2022/06/10
- [PULL 31/54] acpi: pc/q35: tpm-tis: fix TPM device scope, Michael S. Tsirkin, 2022/06/10
- [PULL 33/54] acpi: tpm-tis: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML, Michael S. Tsirkin, 2022/06/10
- [PULL 38/54] hw/cxl: Push linking of CXL targets into i386/pc rather than in machine.c, Michael S. Tsirkin, 2022/06/10
- [PULL 39/54] tests/acpi: Allow modification of q35 CXL CEDT table., Michael S. Tsirkin, 2022/06/10
- [PULL 37/54] hw/acpi/cxl: Pass in the CXLState directly rather than MachineState, Michael S. Tsirkin, 2022/06/10
- [PULL 40/54] pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.,
Michael S. Tsirkin <=
- [PULL 35/54] x86: acpi-build: do not include hw/isa/isa.h directly, Michael S. Tsirkin, 2022/06/10
- [PULL 43/54] hw/machine: Drop cxl_supported flag as no longer useful, Michael S. Tsirkin, 2022/06/10
- [PULL 42/54] hw/cxl: Move the CXLState from MachineState to machine type specific state., Michael S. Tsirkin, 2022/06/10
- [PULL 36/54] hw/cxl: Make the CXL fixed memory window setup a machine parameter., Michael S. Tsirkin, 2022/06/10
- [PULL 41/54] tests/acpi: Update q35/CEDT.cxl for new memory addresses., Michael S. Tsirkin, 2022/06/10
- [PULL 44/54] pci: fix overflow in snprintf string formatting, Michael S. Tsirkin, 2022/06/10
- [PULL 45/54] hw/cxl: Fix missing write mask for HDM decoder target list registers, Michael S. Tsirkin, 2022/06/10
- [PULL 46/54] hw/acpi/viot: rename build_pci_range_node() to enumerate_pci_host_bridges(), Michael S. Tsirkin, 2022/06/10
- [PULL 47/54] hw/acpi/viot: move the individual PCI host bridge entry generation to a new function, Michael S. Tsirkin, 2022/06/10
- [PULL 48/54] hw/acpi/viot: build array of PCI host bridges before generating VIOT ACPI table, Michael S. Tsirkin, 2022/06/10