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[PULL 11/45] target/arm: Mark LDS{MIN,MAX} as signed operations
From: |
Peter Maydell |
Subject: |
[PULL 11/45] target/arm: Mark LDS{MIN,MAX} as signed operations |
Date: |
Thu, 3 Jun 2021 16:58:30 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
The operands to tcg_gen_atomic_fetch_s{min,max}_i64 must
be signed, so that the inputs are properly extended.
Zero extend the result afterward, as needed.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/364
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20210602020720.47679-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ceac0ee2bd6..d6906d9012c 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3355,8 +3355,9 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t
insn,
int o3_opc = extract32(insn, 12, 4);
bool r = extract32(insn, 22, 1);
bool a = extract32(insn, 23, 1);
- TCGv_i64 tcg_rs, clean_addr;
+ TCGv_i64 tcg_rs, tcg_rt, clean_addr;
AtomicThreeOpFn *fn = NULL;
+ MemOp mop = s->be_data | size | MO_ALIGN;
if (is_vector || !dc_isar_feature(aa64_atomics, s)) {
unallocated_encoding(s);
@@ -3377,9 +3378,11 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t
insn,
break;
case 004: /* LDSMAX */
fn = tcg_gen_atomic_fetch_smax_i64;
+ mop |= MO_SIGN;
break;
case 005: /* LDSMIN */
fn = tcg_gen_atomic_fetch_smin_i64;
+ mop |= MO_SIGN;
break;
case 006: /* LDUMAX */
fn = tcg_gen_atomic_fetch_umax_i64;
@@ -3422,6 +3425,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t
insn,
}
tcg_rs = read_cpu_reg(s, rs, true);
+ tcg_rt = cpu_reg(s, rt);
if (o3_opc == 1) { /* LDCLR */
tcg_gen_not_i64(tcg_rs, tcg_rs);
@@ -3430,8 +3434,11 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t
insn,
/* The tcg atomic primitives are all full barriers. Therefore we
* can ignore the Acquire and Release bits of this instruction.
*/
- fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s),
- s->be_data | size | MO_ALIGN);
+ fn(tcg_rt, clean_addr, tcg_rs, get_mem_index(s), mop);
+
+ if ((mop & MO_SIGN) && size != MO_64) {
+ tcg_gen_ext32u_i64(tcg_rt, tcg_rt);
+ }
}
/*
--
2.20.1
- [PULL 01/45] target/arm: Add isar feature check functions for MVE, (continued)
- [PULL 01/45] target/arm: Add isar feature check functions for MVE, Peter Maydell, 2021/06/03
- [PULL 02/45] target/arm: Update feature checks for insns which are "MVE or FP", Peter Maydell, 2021/06/03
- [PULL 03/45] target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp, Peter Maydell, 2021/06/03
- [PULL 04/45] target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp, Peter Maydell, 2021/06/03
- [PULL 06/45] target/arm: Implement M-profile VPR register, Peter Maydell, 2021/06/03
- [PULL 07/45] target/arm: Make FPSCR.LTPSIZE writable for MVE, Peter Maydell, 2021/06/03
- [PULL 05/45] target/arm: Fix return values in fp_sysreg_checks(), Peter Maydell, 2021/06/03
- [PULL 10/45] docs: Fix installation of man pages with Sphinx 4.x, Peter Maydell, 2021/06/03
- [PULL 08/45] target/arm: Allow board models to specify initial NS VTOR, Peter Maydell, 2021/06/03
- [PULL 09/45] arm: Consistently use "Cortex-Axx", not "Cortex Axx", Peter Maydell, 2021/06/03
- [PULL 11/45] target/arm: Mark LDS{MIN,MAX} as signed operations,
Peter Maydell <=
- [PULL 12/45] target/arm: fix missing exception class, Peter Maydell, 2021/06/03
- [PULL 16/45] target/arm: Add isar_feature_{aa32, aa64, aa64_sve}_bf16, Peter Maydell, 2021/06/03
- [PULL 13/45] target/arm: fold do_raise_exception into raise_exception, Peter Maydell, 2021/06/03
- [PULL 14/45] target/arm: use raise_exception_ra for MTE check failure, Peter Maydell, 2021/06/03
- [PULL 20/45] softfpu: Add float_round_to_odd_inf, Peter Maydell, 2021/06/03
- [PULL 18/45] target/arm: Implement scalar float32 to bfloat16 conversion, Peter Maydell, 2021/06/03
- [PULL 15/45] target/arm: use raise_exception_ra for stack limit exception, Peter Maydell, 2021/06/03
- [PULL 17/45] target/arm: Unify unallocated path in disas_fp_1src, Peter Maydell, 2021/06/03
- [PULL 19/45] target/arm: Implement vector float32 to bfloat16 conversion, Peter Maydell, 2021/06/03
- [PULL 21/45] target/arm: Implement bfloat16 dot product (vector), Peter Maydell, 2021/06/03