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[PULL 18/45] target/arm: Implement scalar float32 to bfloat16 conversion
From: |
Peter Maydell |
Subject: |
[PULL 18/45] target/arm: Implement scalar float32 to bfloat16 conversion |
Date: |
Thu, 3 Jun 2021 16:58:37 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
This is the 64-bit BFCVT and the 32-bit VCVT{B,T}.BF16.F32.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.h | 1 +
target/arm/vfp.decode | 2 ++
target/arm/translate-a64.c | 19 +++++++++++++++++++
target/arm/translate-vfp.c | 24 ++++++++++++++++++++++++
target/arm/vfp_helper.c | 5 +++++
5 files changed, 51 insertions(+)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 23ccb0f72f6..9977a827e97 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -143,6 +143,7 @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
+DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, ptr)
DEF_HELPER_2(vfp_uitoh, f16, i32, ptr)
DEF_HELPER_2(vfp_uitos, f32, i32, ptr)
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 6f7f28f9a46..52535d9b0b8 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -205,6 +205,8 @@ VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \
# VCVTB and VCVTT to f16: Vd format is always vd_sp;
# Vm format depends on size bit
+VCVT_b16_f32 ---- 1110 1.11 0011 .... 1001 t:1 1.0 .... \
+ vd=%vd_sp vm=%vm_sp
VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \
vd=%vd_sp vm=%vm_sp
VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 95c2853f39f..b335ca87355 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6280,6 +6280,9 @@ static void handle_fp_1src_single(DisasContext *s, int
opcode, int rd, int rn)
case 0x3: /* FSQRT */
gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
goto done;
+ case 0x6: /* BFCVT */
+ gen_fpst = gen_helper_bfcvt;
+ break;
case 0x8: /* FRINTN */
case 0x9: /* FRINTP */
case 0xa: /* FRINTM */
@@ -6557,6 +6560,22 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
}
break;
+ case 0x6:
+ switch (type) {
+ case 1: /* BFCVT */
+ if (!dc_isar_feature(aa64_bf16, s)) {
+ goto do_unallocated;
+ }
+ if (!fp_access_check(s)) {
+ return;
+ }
+ handle_fp_1src_single(s, opcode, rd, rn);
+ break;
+ default:
+ goto do_unallocated;
+ }
+ break;
+
default:
do_unallocated:
unallocated_encoding(s);
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index 2316e105acc..d01e465821b 100644
--- a/target/arm/translate-vfp.c
+++ b/target/arm/translate-vfp.c
@@ -3085,6 +3085,30 @@ static bool trans_VCVT_f64_f16(DisasContext *s,
arg_VCVT_f64_f16 *a)
return true;
}
+static bool trans_VCVT_b16_f32(DisasContext *s, arg_VCVT_b16_f32 *a)
+{
+ TCGv_ptr fpst;
+ TCGv_i32 tmp;
+
+ if (!dc_isar_feature(aa32_bf16, s)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = fpstatus_ptr(FPST_FPCR);
+ tmp = tcg_temp_new_i32();
+
+ vfp_load_reg32(tmp, a->vm);
+ gen_helper_bfcvt(tmp, tmp, fpst);
+ tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i32(tmp);
+ return true;
+}
+
static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a)
{
TCGv_ptr fpst;
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index e0886ab5a56..200439ad663 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -411,6 +411,11 @@ float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
return float64_to_float32(x, &env->vfp.fp_status);
}
+uint32_t HELPER(bfcvt)(float32 x, void *status)
+{
+ return float32_to_bfloat16(x, status);
+}
+
/*
* VFP3 fixed point conversion. The AArch32 versions of fix-to-float
* must always round-to-nearest; the AArch64 ones honour the FPSCR
--
2.20.1
- [PULL 05/45] target/arm: Fix return values in fp_sysreg_checks(), (continued)
- [PULL 05/45] target/arm: Fix return values in fp_sysreg_checks(), Peter Maydell, 2021/06/03
- [PULL 10/45] docs: Fix installation of man pages with Sphinx 4.x, Peter Maydell, 2021/06/03
- [PULL 08/45] target/arm: Allow board models to specify initial NS VTOR, Peter Maydell, 2021/06/03
- [PULL 09/45] arm: Consistently use "Cortex-Axx", not "Cortex Axx", Peter Maydell, 2021/06/03
- [PULL 11/45] target/arm: Mark LDS{MIN,MAX} as signed operations, Peter Maydell, 2021/06/03
- [PULL 12/45] target/arm: fix missing exception class, Peter Maydell, 2021/06/03
- [PULL 16/45] target/arm: Add isar_feature_{aa32, aa64, aa64_sve}_bf16, Peter Maydell, 2021/06/03
- [PULL 13/45] target/arm: fold do_raise_exception into raise_exception, Peter Maydell, 2021/06/03
- [PULL 14/45] target/arm: use raise_exception_ra for MTE check failure, Peter Maydell, 2021/06/03
- [PULL 20/45] softfpu: Add float_round_to_odd_inf, Peter Maydell, 2021/06/03
- [PULL 18/45] target/arm: Implement scalar float32 to bfloat16 conversion,
Peter Maydell <=
- [PULL 15/45] target/arm: use raise_exception_ra for stack limit exception, Peter Maydell, 2021/06/03
- [PULL 17/45] target/arm: Unify unallocated path in disas_fp_1src, Peter Maydell, 2021/06/03
- [PULL 19/45] target/arm: Implement vector float32 to bfloat16 conversion, Peter Maydell, 2021/06/03
- [PULL 21/45] target/arm: Implement bfloat16 dot product (vector), Peter Maydell, 2021/06/03
- [PULL 22/45] target/arm: Implement bfloat16 dot product (indexed), Peter Maydell, 2021/06/03
- [PULL 23/45] target/arm: Implement bfloat16 matrix multiply accumulate, Peter Maydell, 2021/06/03
- [PULL 24/45] target/arm: Implement bfloat widening fma (vector), Peter Maydell, 2021/06/03
- [PULL 26/45] linux-user/aarch64: Enable hwcap bits for bfloat16, Peter Maydell, 2021/06/03
- [PULL 25/45] target/arm: Implement bfloat widening fma (indexed), Peter Maydell, 2021/06/03
- [PULL 27/45] target/arm: Enable BFloat16 extensions, Peter Maydell, 2021/06/03