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[PULL 07/45] target/arm: Make FPSCR.LTPSIZE writable for MVE
From: |
Peter Maydell |
Subject: |
[PULL 07/45] target/arm: Make FPSCR.LTPSIZE writable for MVE |
Date: |
Thu, 3 Jun 2021 16:58:26 +0100 |
The M-profile FPSCR has an LTPSIZE field, but if MVE is not
implemented it is read-only and always reads as 4; this is how QEMU
currently handles it.
Make the field writable when MVE is implemented.
We can safely add the field to the MVE migration struct because
currently no CPUs enable MVE and so the migration struct is never
used.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520152840.24453-8-peter.maydell@linaro.org
---
target/arm/cpu.h | 3 ++-
target/arm/machine.c | 1 +
target/arm/vfp_helper.c | 9 ++++++---
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index df2f189c49b..c389b1e9691 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -563,7 +563,7 @@ typedef struct CPUARMState {
uint32_t fpdscr[M_REG_NUM_BANKS];
uint32_t cpacr[M_REG_NUM_BANKS];
uint32_t nsacr;
- int ltpsize;
+ uint32_t ltpsize;
uint32_t vpr;
} v7m;
@@ -1562,6 +1562,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
#define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
+#define FPCR_LTPSIZE_LENGTH 3
#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 62a71a3b640..81e30de8243 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -332,6 +332,7 @@ static const VMStateDescription vmstate_m_mve = {
.needed = mve_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT32(env.v7m.vpr, ARMCPU),
+ VMSTATE_UINT32(env.v7m.ltpsize, ARMCPU),
VMSTATE_END_OF_LIST()
},
};
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 01b9d8557f7..e0886ab5a56 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -195,8 +195,10 @@ uint32_t vfp_get_fpscr(CPUARMState *env)
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
{
+ ARMCPU *cpu = env_archcpu(env);
+
/* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
- if (!cpu_isar_feature(any_fp16, env_archcpu(env))) {
+ if (!cpu_isar_feature(any_fp16, cpu)) {
val &= ~FPCR_FZ16;
}
@@ -210,11 +212,12 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
* because in v7A no-short-vector-support cores still had to
* allow Stride/Len to be written with the only effect that
* some insns are required to UNDEF if the guest sets them.
- *
- * TODO: if M-profile MVE implemented, set LTPSIZE.
*/
env->vfp.vec_len = extract32(val, 16, 3);
env->vfp.vec_stride = extract32(val, 20, 2);
+ } else if (cpu_isar_feature(aa32_mve, cpu)) {
+ env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT,
+ FPCR_LTPSIZE_LENGTH);
}
if (arm_feature(env, ARM_FEATURE_NEON)) {
--
2.20.1
- [PULL 00/45] target-arm queue, Peter Maydell, 2021/06/03
- [PULL 01/45] target/arm: Add isar feature check functions for MVE, Peter Maydell, 2021/06/03
- [PULL 02/45] target/arm: Update feature checks for insns which are "MVE or FP", Peter Maydell, 2021/06/03
- [PULL 03/45] target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp, Peter Maydell, 2021/06/03
- [PULL 04/45] target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp, Peter Maydell, 2021/06/03
- [PULL 06/45] target/arm: Implement M-profile VPR register, Peter Maydell, 2021/06/03
- [PULL 07/45] target/arm: Make FPSCR.LTPSIZE writable for MVE,
Peter Maydell <=
- [PULL 05/45] target/arm: Fix return values in fp_sysreg_checks(), Peter Maydell, 2021/06/03
- [PULL 10/45] docs: Fix installation of man pages with Sphinx 4.x, Peter Maydell, 2021/06/03
- [PULL 08/45] target/arm: Allow board models to specify initial NS VTOR, Peter Maydell, 2021/06/03
- [PULL 09/45] arm: Consistently use "Cortex-Axx", not "Cortex Axx", Peter Maydell, 2021/06/03
- [PULL 11/45] target/arm: Mark LDS{MIN,MAX} as signed operations, Peter Maydell, 2021/06/03
- [PULL 12/45] target/arm: fix missing exception class, Peter Maydell, 2021/06/03
- [PULL 16/45] target/arm: Add isar_feature_{aa32, aa64, aa64_sve}_bf16, Peter Maydell, 2021/06/03
- [PULL 13/45] target/arm: fold do_raise_exception into raise_exception, Peter Maydell, 2021/06/03
- [PULL 14/45] target/arm: use raise_exception_ra for MTE check failure, Peter Maydell, 2021/06/03
- [PULL 20/45] softfpu: Add float_round_to_odd_inf, Peter Maydell, 2021/06/03