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[PULL 00/45] target-arm queue
From: |
Peter Maydell |
Subject: |
[PULL 00/45] target-arm queue |
Date: |
Thu, 3 Jun 2021 16:58:19 +0100 |
The following changes since commit a97978bcc2d1f650c7d411428806e5b03082b8c7:
Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.1-20210603'
into staging (2021-06-03 10:00:35 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20210603
for you to fetch changes up to 1c861885894d840235954060050d240259f5340b:
tests/unit/test-vmstate: Assert that dup() and mkstemp() succeed (2021-06-03
16:43:27 +0100)
----------------------------------------------------------------
target-arm queue:
* Some not-yet-enabled preliminaries for M-profile MVE support
* Consistently use "Cortex-Axx", not "Cortex Axx" in docs, comments
* docs: Fix installation of man pages with Sphinx 4.x
* Mark LDS{MIN,MAX} as signed operations
* Fix missing syndrome value for DAIF and PAC check exceptions
* Implement BFloat16 extensions
* Refactoring of hvf accelerator code in preparation for aarch64 support
* Fix some coverity nits in test code
----------------------------------------------------------------
Alexander Graf (12):
hvf: Move assert_hvf_ok() into common directory
hvf: Move vcpu thread functions into common directory
hvf: Move cpu functions into common directory
hvf: Move hvf internal definitions into common header
hvf: Make hvf_set_phys_mem() static
hvf: Remove use of hv_uvaddr_t and hv_gpaddr_t
hvf: Split out common code on vcpu init and destroy
hvf: Use cpu_synchronize_state()
hvf: Make synchronize functions static
hvf: Remove hvf-accel-ops.h
hvf: Introduce hvf vcpu struct
hvf: Simplify post reset/init/loadvm hooks
Damien Goutte-Gattat (1):
docs: Fix installation of man pages with Sphinx 4.x
Jamie Iles (4):
target/arm: fix missing exception class
target/arm: fold do_raise_exception into raise_exception
target/arm: use raise_exception_ra for MTE check failure
target/arm: use raise_exception_ra for stack limit exception
Peter Maydell (15):
target/arm: Add isar feature check functions for MVE
target/arm: Update feature checks for insns which are "MVE or FP"
target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp
target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp
target/arm: Fix return values in fp_sysreg_checks()
target/arm: Implement M-profile VPR register
target/arm: Make FPSCR.LTPSIZE writable for MVE
target/arm: Allow board models to specify initial NS VTOR
arm: Consistently use "Cortex-Axx", not "Cortex Axx"
tests/qtest/bios-tables-test: Check for dup2() failure
tests/qtest/e1000e-test: Check qemu_recv() succeeded
tests/qtest/hd-geo-test: Fix checks on mkstemp() return value
tests/qtest/pflash-cfi02-test: Avoid potential integer overflow
tests/qtest/tpm-tests: Remove unnecessary NULL checks
tests/unit/test-vmstate: Assert that dup() and mkstemp() succeed
Richard Henderson (13):
target/arm: Mark LDS{MIN,MAX} as signed operations
target/arm: Add isar_feature_{aa32, aa64, aa64_sve}_bf16
target/arm: Unify unallocated path in disas_fp_1src
target/arm: Implement scalar float32 to bfloat16 conversion
target/arm: Implement vector float32 to bfloat16 conversion
softfpu: Add float_round_to_odd_inf
target/arm: Implement bfloat16 dot product (vector)
target/arm: Implement bfloat16 dot product (indexed)
target/arm: Implement bfloat16 matrix multiply accumulate
target/arm: Implement bfloat widening fma (vector)
target/arm: Implement bfloat widening fma (indexed)
linux-user/aarch64: Enable hwcap bits for bfloat16
target/arm: Enable BFloat16 extensions
docs/conf.py | 1 +
docs/system/arm/aspeed.rst | 4 +-
docs/system/arm/nuvoton.rst | 6 +-
docs/system/arm/sabrelite.rst | 2 +-
include/fpu/softfloat-types.h | 4 +-
include/hw/arm/allwinner-h3.h | 2 +-
include/hw/arm/armv7m.h | 2 +
include/hw/core/cpu.h | 3 +-
include/sysemu/hvf_int.h | 58 +++++
target/arm/cpu.h | 48 +++-
target/arm/helper-sve.h | 4 +
target/arm/helper.h | 15 ++
target/i386/hvf/hvf-accel-ops.h | 23 --
target/i386/hvf/hvf-i386.h | 33 +--
target/i386/hvf/vmx.h | 24 +-
target/i386/hvf/x86hvf.h | 2 -
target/arm/neon-dp.decode | 1 +
target/arm/neon-shared.decode | 11 +
target/arm/sve.decode | 19 +-
target/arm/vfp.decode | 2 +
accel/hvf/hvf-accel-ops.c | 471 ++++++++++++++++++++++++++++++++++++++++
accel/hvf/hvf-all.c | 47 ++++
hw/arm/armv7m.c | 7 +
hw/arm/aspeed.c | 6 +-
hw/arm/mcimx6ul-evk.c | 2 +-
hw/arm/mcimx7d-sabre.c | 2 +-
hw/arm/npcm7xx_boards.c | 4 +-
hw/arm/sabrelite.c | 2 +-
hw/misc/npcm7xx_clk.c | 2 +-
linux-user/elfload.c | 2 +
target/arm/cpu.c | 13 ++
target/arm/cpu64.c | 3 +
target/arm/cpu_tcg.c | 1 +
target/arm/m_helper.c | 5 +-
target/arm/machine.c | 20 ++
target/arm/mte_helper.c | 12 +-
target/arm/op_helper.c | 32 ++-
target/arm/sve_helper.c | 2 +
target/arm/translate-a64.c | 155 +++++++++++--
target/arm/translate-neon.c | 91 ++++++++
target/arm/translate-sve.c | 112 ++++++++++
target/arm/translate-vfp.c | 164 ++++++++++----
target/arm/vec_helper.c | 140 +++++++++++-
target/arm/vfp_helper.c | 21 +-
target/i386/hvf/hvf-accel-ops.c | 146 -------------
target/i386/hvf/hvf.c | 464 +++++----------------------------------
target/i386/hvf/x86.c | 28 +--
target/i386/hvf/x86_descr.c | 26 +--
target/i386/hvf/x86_emu.c | 62 +++---
target/i386/hvf/x86_mmu.c | 4 +-
target/i386/hvf/x86_task.c | 12 +-
target/i386/hvf/x86hvf.c | 222 +++++++++----------
tests/qtest/bios-tables-test.c | 8 +-
tests/qtest/e1000e-test.c | 3 +-
tests/qtest/hd-geo-test.c | 4 +-
tests/qtest/pflash-cfi02-test.c | 2 +-
tests/qtest/tpm-tests.c | 12 +-
tests/unit/test-vmstate.c | 5 +-
fpu/softfloat-parts.c.inc | 6 +-
MAINTAINERS | 8 +
accel/hvf/meson.build | 7 +
accel/meson.build | 1 +
target/i386/hvf/meson.build | 1 -
63 files changed, 1666 insertions(+), 935 deletions(-)
create mode 100644 include/sysemu/hvf_int.h
delete mode 100644 target/i386/hvf/hvf-accel-ops.h
create mode 100644 accel/hvf/hvf-accel-ops.c
create mode 100644 accel/hvf/hvf-all.c
delete mode 100644 target/i386/hvf/hvf-accel-ops.c
create mode 100644 accel/hvf/meson.build
- [PULL 00/45] target-arm queue,
Peter Maydell <=
- [PULL 01/45] target/arm: Add isar feature check functions for MVE, Peter Maydell, 2021/06/03
- [PULL 02/45] target/arm: Update feature checks for insns which are "MVE or FP", Peter Maydell, 2021/06/03
- [PULL 03/45] target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp, Peter Maydell, 2021/06/03
- [PULL 04/45] target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp, Peter Maydell, 2021/06/03
- [PULL 06/45] target/arm: Implement M-profile VPR register, Peter Maydell, 2021/06/03
- [PULL 07/45] target/arm: Make FPSCR.LTPSIZE writable for MVE, Peter Maydell, 2021/06/03
- [PULL 05/45] target/arm: Fix return values in fp_sysreg_checks(), Peter Maydell, 2021/06/03
- [PULL 10/45] docs: Fix installation of man pages with Sphinx 4.x, Peter Maydell, 2021/06/03
- [PULL 08/45] target/arm: Allow board models to specify initial NS VTOR, Peter Maydell, 2021/06/03
- [PULL 09/45] arm: Consistently use "Cortex-Axx", not "Cortex Axx", Peter Maydell, 2021/06/03