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[PULL 108/114] target/arm: Fix decode for VDOT (indexed)
From: |
Peter Maydell |
Subject: |
[PULL 108/114] target/arm: Fix decode for VDOT (indexed) |
Date: |
Tue, 25 May 2021 16:07:30 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
We were extracting the M register twice, once incorrectly
as M:vm and once correctly as rm. Remove the incorrect
name and remove the incorrect decode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-87-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/neon-shared.decode | 4 ++--
target/arm/translate-neon.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index ca0c699072e..facb621450d 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -61,8 +61,8 @@ VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1
index:1 0 vm:4 \
VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp size=2 index=0
-VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 vm:4 \
+ vn=%vn_dp vd=%vd_dp
%vfml_scalar_q0_rm 0:3 5:1
%vfml_scalar_q1_index 5:1 3:1
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index 14a9d0d4d30..9f7a88aab1b 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -348,7 +348,7 @@ static bool trans_VDOT_scalar(DisasContext *s,
arg_VDOT_scalar *a)
opr_sz = (1 + a->q) * 8;
tcg_gen_gvec_4_ool(vfp_reg_offset(1, a->vd),
vfp_reg_offset(1, a->vn),
- vfp_reg_offset(1, a->rm),
+ vfp_reg_offset(1, a->vm),
vfp_reg_offset(1, a->vd),
opr_sz, opr_sz, a->index, fn_gvec);
return true;
--
2.20.1
- [PULL 095/114] target/arm: Implement SVE2 FCVTLT, Peter Maydell, 2021/05/25
- [PULL 096/114] target/arm: Implement SVE2 FCVTXNT, FCVTX, Peter Maydell, 2021/05/25
- [PULL 099/114] target/arm: Tidy do_ldrq, Peter Maydell, 2021/05/25
- [PULL 100/114] target/arm: Implement SVE2 LD1RO, Peter Maydell, 2021/05/25
- [PULL 103/114] target/arm: Move endian adjustment macros to vec_internal.h, Peter Maydell, 2021/05/25
- [PULL 102/114] target/arm: Implement SVE2 bitwise shift immediate, Peter Maydell, 2021/05/25
- [PULL 106/114] target/arm: Split out do_neon_ddda_fpst, Peter Maydell, 2021/05/25
- [PULL 108/114] target/arm: Fix decode for VDOT (indexed),
Peter Maydell <=
- [PULL 109/114] target/arm: Split out do_neon_ddda, Peter Maydell, 2021/05/25
- [PULL 101/114] target/arm: Implement 128-bit ZIP, UZP, TRN, Peter Maydell, 2021/05/25
- [PULL 104/114] target/arm: Implement SVE2 fp multiply-add long, Peter Maydell, 2021/05/25
- [PULL 105/114] target/arm: Implement aarch64 SUDOT, USDOT, Peter Maydell, 2021/05/25
- [PULL 110/114] target/arm: Split decode of VSDOT and VUDOT, Peter Maydell, 2021/05/25
- [PULL 114/114] target/arm: Enable SVE2 and related extensions, Peter Maydell, 2021/05/25
- [PULL 107/114] target/arm: Remove unused fpst from VDOT_scalar, Peter Maydell, 2021/05/25
- [PULL 112/114] target/arm: Implement integer matrix multiply accumulate, Peter Maydell, 2021/05/25
- [PULL 113/114] linux-user/aarch64: Enable hwcap bits for sve2 and related extensions, Peter Maydell, 2021/05/25
- [PULL 098/114] target/arm: Share table of sve load functions, Peter Maydell, 2021/05/25