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[PULL 103/114] target/arm: Move endian adjustment macros to vec_internal
From: |
Peter Maydell |
Subject: |
[PULL 103/114] target/arm: Move endian adjustment macros to vec_internal.h |
Date: |
Tue, 25 May 2021 16:07:25 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
We have two copies of these, one set of which is not complete.
Move them to a common header.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-82-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/vec_internal.h | 24 ++++++++++++++++++++++++
target/arm/sve_helper.c | 16 ----------------
target/arm/vec_helper.c | 12 ------------
3 files changed, 24 insertions(+), 28 deletions(-)
diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h
index ff694d870ac..dba481e0012 100644
--- a/target/arm/vec_internal.h
+++ b/target/arm/vec_internal.h
@@ -20,6 +20,30 @@
#ifndef TARGET_ARM_VEC_INTERNALS_H
#define TARGET_ARM_VEC_INTERNALS_H
+/*
+ * Note that vector data is stored in host-endian 64-bit chunks,
+ * so addressing units smaller than that needs a host-endian fixup.
+ *
+ * The H<N> macros are used when indexing an array of elements of size N.
+ *
+ * The H1_<N> macros are used when performing byte arithmetic and then
+ * casting the final pointer to a type of size N.
+ */
+#ifdef HOST_WORDS_BIGENDIAN
+#define H1(x) ((x) ^ 7)
+#define H1_2(x) ((x) ^ 6)
+#define H1_4(x) ((x) ^ 4)
+#define H2(x) ((x) ^ 3)
+#define H4(x) ((x) ^ 1)
+#else
+#define H1(x) (x)
+#define H1_2(x) (x)
+#define H1_4(x) (x)
+#define H2(x) (x)
+#define H4(x) (x)
+#endif
+
+
static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
{
uint64_t *d = vd + opr_sz;
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 4afb06fb2a1..40af3024dfb 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -29,22 +29,6 @@
#include "vec_internal.h"
-/* Note that vector data is stored in host-endian 64-bit chunks,
- so addressing units smaller than that needs a host-endian fixup. */
-#ifdef HOST_WORDS_BIGENDIAN
-#define H1(x) ((x) ^ 7)
-#define H1_2(x) ((x) ^ 6)
-#define H1_4(x) ((x) ^ 4)
-#define H2(x) ((x) ^ 3)
-#define H4(x) ((x) ^ 1)
-#else
-#define H1(x) (x)
-#define H1_2(x) (x)
-#define H1_4(x) (x)
-#define H2(x) (x)
-#define H4(x) (x)
-#endif
-
/* Return a value for NZCV as per the ARM PredTest pseudofunction.
*
* The return value has bit 31 set if N is set, bit 1 set if Z is clear,
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index 21ae1258f2e..f5af45375df 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -25,18 +25,6 @@
#include "qemu/int128.h"
#include "vec_internal.h"
-/* Note that vector data is stored in host-endian 64-bit chunks,
- so addressing units smaller than that needs a host-endian fixup. */
-#ifdef HOST_WORDS_BIGENDIAN
-#define H1(x) ((x) ^ 7)
-#define H2(x) ((x) ^ 3)
-#define H4(x) ((x) ^ 1)
-#else
-#define H1(x) (x)
-#define H2(x) (x)
-#define H4(x) (x)
-#endif
-
/* Signed saturating rounding doubling multiply-accumulate high half, 8-bit */
int8_t do_sqrdmlah_b(int8_t src1, int8_t src2, int8_t src3,
bool neg, bool round)
--
2.20.1
- [PULL 095/114] target/arm: Implement SVE2 FCVTLT, Peter Maydell, 2021/05/25
- [PULL 096/114] target/arm: Implement SVE2 FCVTXNT, FCVTX, Peter Maydell, 2021/05/25
- [PULL 099/114] target/arm: Tidy do_ldrq, Peter Maydell, 2021/05/25
- [PULL 100/114] target/arm: Implement SVE2 LD1RO, Peter Maydell, 2021/05/25
- [PULL 103/114] target/arm: Move endian adjustment macros to vec_internal.h,
Peter Maydell <=
- [PULL 102/114] target/arm: Implement SVE2 bitwise shift immediate, Peter Maydell, 2021/05/25
- [PULL 106/114] target/arm: Split out do_neon_ddda_fpst, Peter Maydell, 2021/05/25
- [PULL 108/114] target/arm: Fix decode for VDOT (indexed), Peter Maydell, 2021/05/25
- [PULL 109/114] target/arm: Split out do_neon_ddda, Peter Maydell, 2021/05/25
- [PULL 101/114] target/arm: Implement 128-bit ZIP, UZP, TRN, Peter Maydell, 2021/05/25
- [PULL 104/114] target/arm: Implement SVE2 fp multiply-add long, Peter Maydell, 2021/05/25
- [PULL 105/114] target/arm: Implement aarch64 SUDOT, USDOT, Peter Maydell, 2021/05/25
- [PULL 110/114] target/arm: Split decode of VSDOT and VUDOT, Peter Maydell, 2021/05/25
- [PULL 114/114] target/arm: Enable SVE2 and related extensions, Peter Maydell, 2021/05/25
- [PULL 107/114] target/arm: Remove unused fpst from VDOT_scalar, Peter Maydell, 2021/05/25