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[PULL 110/114] target/arm: Split decode of VSDOT and VUDOT
From: |
Peter Maydell |
Subject: |
[PULL 110/114] target/arm: Split decode of VSDOT and VUDOT |
Date: |
Tue, 25 May 2021 16:07:32 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Now that we have a common helper, sharing decode does not
save much. Also, this will solve an upcoming naming problem.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-89-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/neon-shared.decode | 9 ++++++---
target/arm/translate-neon.c | 30 ++++++++++++++++++++++--------
2 files changed, 28 insertions(+), 11 deletions(-)
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index facb621450d..2d94369750d 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -46,8 +46,9 @@ VCMLA 1111 110 rot:2 . 1 . .... .... 1000 . q:1 . 0
.... \
VCADD 1111 110 rot:1 1 . 0 . .... .... 1000 . q:1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%vcadd_size
-# VUDOT and VSDOT
-VDOT 1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \
+VSDOT 1111 110 00 . 10 .... .... 1101 . q:1 . 0 .... \
+ vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VUDOT 1111 110 00 . 10 .... .... 1101 . q:1 . 1 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp
# VFM[AS]L
@@ -61,7 +62,9 @@ VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1
index:1 0 vm:4 \
VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp size=2 index=0
-VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 vm:4 \
+VSDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 0 vm:4 \
+ vn=%vn_dp vd=%vd_dp
+VUDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 1 vm:4 \
vn=%vn_dp vd=%vd_dp
%vfml_scalar_q0_rm 0:3 5:1
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index dfa33912ab1..386b42fe4b0 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -269,15 +269,22 @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
return true;
}
-static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
+static bool trans_VSDOT(DisasContext *s, arg_VSDOT *a)
{
if (!dc_isar_feature(aa32_dp, s)) {
return false;
}
return do_neon_ddda(s, a->q * 7, a->vd, a->vn, a->vm, 0,
- a->u
- ? gen_helper_gvec_udot_b
- : gen_helper_gvec_sdot_b);
+ gen_helper_gvec_sdot_b);
+}
+
+static bool trans_VUDOT(DisasContext *s, arg_VUDOT *a)
+{
+ if (!dc_isar_feature(aa32_dp, s)) {
+ return false;
+ }
+ return do_neon_ddda(s, a->q * 7, a->vd, a->vn, a->vm, 0,
+ gen_helper_gvec_udot_b);
}
static bool trans_VFML(DisasContext *s, arg_VFML *a)
@@ -329,15 +336,22 @@ static bool trans_VCMLA_scalar(DisasContext *s,
arg_VCMLA_scalar *a)
FPST_STD, gen_helper_gvec_fcmlas_idx);
}
-static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
+static bool trans_VSDOT_scalar(DisasContext *s, arg_VSDOT_scalar *a)
{
if (!dc_isar_feature(aa32_dp, s)) {
return false;
}
return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index,
- a->u
- ? gen_helper_gvec_udot_idx_b
- : gen_helper_gvec_sdot_idx_b);
+ gen_helper_gvec_sdot_idx_b);
+}
+
+static bool trans_VUDOT_scalar(DisasContext *s, arg_VUDOT_scalar *a)
+{
+ if (!dc_isar_feature(aa32_dp, s)) {
+ return false;
+ }
+ return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index,
+ gen_helper_gvec_udot_idx_b);
}
static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
--
2.20.1
- [PULL 099/114] target/arm: Tidy do_ldrq, (continued)
- [PULL 099/114] target/arm: Tidy do_ldrq, Peter Maydell, 2021/05/25
- [PULL 100/114] target/arm: Implement SVE2 LD1RO, Peter Maydell, 2021/05/25
- [PULL 103/114] target/arm: Move endian adjustment macros to vec_internal.h, Peter Maydell, 2021/05/25
- [PULL 102/114] target/arm: Implement SVE2 bitwise shift immediate, Peter Maydell, 2021/05/25
- [PULL 106/114] target/arm: Split out do_neon_ddda_fpst, Peter Maydell, 2021/05/25
- [PULL 108/114] target/arm: Fix decode for VDOT (indexed), Peter Maydell, 2021/05/25
- [PULL 109/114] target/arm: Split out do_neon_ddda, Peter Maydell, 2021/05/25
- [PULL 101/114] target/arm: Implement 128-bit ZIP, UZP, TRN, Peter Maydell, 2021/05/25
- [PULL 104/114] target/arm: Implement SVE2 fp multiply-add long, Peter Maydell, 2021/05/25
- [PULL 105/114] target/arm: Implement aarch64 SUDOT, USDOT, Peter Maydell, 2021/05/25
- [PULL 110/114] target/arm: Split decode of VSDOT and VUDOT,
Peter Maydell <=
- [PULL 114/114] target/arm: Enable SVE2 and related extensions, Peter Maydell, 2021/05/25
- [PULL 107/114] target/arm: Remove unused fpst from VDOT_scalar, Peter Maydell, 2021/05/25
- [PULL 112/114] target/arm: Implement integer matrix multiply accumulate, Peter Maydell, 2021/05/25
- [PULL 113/114] linux-user/aarch64: Enable hwcap bits for sve2 and related extensions, Peter Maydell, 2021/05/25
- [PULL 098/114] target/arm: Share table of sve load functions, Peter Maydell, 2021/05/25
- [PULL 097/114] target/arm: Implement SVE2 FLOGB, Peter Maydell, 2021/05/25
- [PULL 111/114] target/arm: Implement aarch32 VSUDOT, VUSDOT, Peter Maydell, 2021/05/25