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[Bug 1923861] Re: Hardfault when accessing FPSCR register

From: Peter Maydell
Subject: [Bug 1923861] Re: Hardfault when accessing FPSCR register
Date: Fri, 16 Apr 2021 09:20:39 -0000

Some of those ID register differences are expected; some I'm surprised by. The 
differences are:
 * no MVE (expected, we don't implement it yet)
 * no double-precision
 * no FP16

So the missing double-precision is why your vcvt UNDEFs. Those last two
ought to be present, but something is squashing them; I will

The FPSCR difference is that we aren't reporting FPSCR.LTPSIZE for some
reason -- that's a bug too.

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  Hardfault when accessing FPSCR register

Status in QEMU:

Bug description:
  QEMU release version: v6.0.0-rc2

  command line:
  qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf 
-semihosting -semihosting-config enable=on,target=native

  host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
  WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64

  guest operating system: none (bare metal)

  I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 
machine. In the startup code I am accessing the FPSCR core register:

      unsigned int fpscr =__get_FPSCR();
      fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);

  where the register access functions __get_FPSCR() and
  __set_FPSCR(fpscr) are taken from CMSIS_5 at

  I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
  same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).

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