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[Bug 1923861] Re: Hardfault when accessing FPSCR register

From: Peter Maydell
Subject: [Bug 1923861] Re: Hardfault when accessing FPSCR register
Date: Thu, 15 Apr 2021 18:17:30 -0000

Thanks. This is a bug in the AN547 model -- we were accidentally turning
off the FPU. I'll write a patch.

NB that with that bug fixed your code then hits an UNDEF trying to do:
  0x00000996:  eef7 1a10  vmrs     r1, mvfr0

Only A-profile CPUs have MVFR0 accessible via the vmrs instruction. For
M-profile this register is memory-mapped, at 0xE000EF40.

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  Hardfault when accessing FPSCR register

Status in QEMU:

Bug description:
  QEMU release version: v6.0.0-rc2

  command line:
  qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf 
-semihosting -semihosting-config enable=on,target=native

  host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
  WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64

  guest operating system: none (bare metal)

  I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 
machine. In the startup code I am accessing the FPSCR core register:

      unsigned int fpscr =__get_FPSCR();
      fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);

  where the register access functions __get_FPSCR() and
  __set_FPSCR(fpscr) are taken from CMSIS_5 at

  I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
  same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).

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