[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Bug 1923861] Re: Hardfault when accessing FPSCR register

From: ml-0
Subject: [Bug 1923861] Re: Hardfault when accessing FPSCR register
Date: Thu, 15 Apr 2021 15:36:30 -0000

Yes, I think I did:

    SCB->NSACR |= (3U << 10U);                /* enable Non-secure access to 
CP10 and CP11 coprocessors */

    SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */
                   (3U << 11U*2U)  );         /* enable CP11 Full Access */

But I get a NOCP (no coprocessor) hard fault.

Does the qemu mps3-an547 model contain the FPU by default or do I have to 
select it via the command line?
Is there an example code / test case included in the qemu database where I can 
lookup the usage of mps3-an547 + FPU?

You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.

  Hardfault when accessing FPSCR register

Status in QEMU:

Bug description:
  QEMU release version: v6.0.0-rc2

  command line:
  qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf 
-semihosting -semihosting-config enable=on,target=native

  host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
  WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64

  guest operating system: none (bare metal)

  I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 
machine. In the startup code I am accessing the FPSCR core register:

      unsigned int fpscr =__get_FPSCR();
      fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);

  where the register access functions __get_FPSCR() and
  __set_FPSCR(fpscr) are taken from CMSIS_5 at

  I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
  same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).

To manage notifications about this bug go to:

reply via email to

[Prev in Thread] Current Thread [Next in Thread]