[Bug 1923861] Re: Hardfault when accessing FPSCR register

[ml-0]

Thanks for the fix. I applied it and
1. yes, the hard fault when reading FPSCR is gone.
2. yes, I also see the UNDEF. Note that on the Corstone-300 MPS3-AN547 FVP I 
can access mvfr0 via vmrs.

I changed the vmrs to ldr. Now I can read the registers. The values differ from 
what the FVP tells me:
fpscr = 0x00000000 (qemu-system-arm) - 0x00040000 (Corstone FVP)
mvfr0 = 0x10110021                   - 0x10110221
mvfr1 = 0x11000011                   - 0x12100211
mvfr2 = 0x00000040                   - 0x00000040

Using the FPU for some simple calculations

    volatile int nom_i, den_i;
    nom_i = 7;
    den_i = 3;
    volatile float nom_f, den_f, div_f;
    nom_f = (float)nom_i;
    den_f = (float)den_i;
    div_f = nom_f / den_f;
    printf("%e / %f = %f\r\n", nom_f, den_f, div_f);

I run into another UNDEF when executing 
    vcvt.f64.f32    d6, s12

Again, the FVP can execute the same elf. I attached it. Maybe you can
have another look.

** Attachment added: "test2.elf"
   
https://bugs.launchpad.net/qemu/+bug/1923861/+attachment/5488742/+files/test2.elf

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https://bugs.launchpad.net/bugs/1923861

Title:
  Hardfault when accessing FPSCR register

Status in QEMU:
  New

Bug description:
  QEMU release version: v6.0.0-rc2

  command line:
  qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf 
-semihosting -semihosting-config enable=on,target=native

  host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
  WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
  GNU/Linux

  guest operating system: none (bare metal)

  Observation:
  I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 
machine. In the startup code I am accessing the FPSCR core register:

      unsigned int fpscr =__get_FPSCR();
      fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
      __set_FPSCR(fpscr);

  where the register access functions __get_FPSCR() and
  __set_FPSCR(fpscr) are taken from CMSIS_5 at
  ./CMSIS/Core/include/cmsis_gcc.h

  I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
  same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).

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