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[RFC v9 36/50] Revert "target/arm: Restrict v8M IDAU to TCG"
From: |
Claudio Fontana |
Subject: |
[RFC v9 36/50] Revert "target/arm: Restrict v8M IDAU to TCG" |
Date: |
Wed, 17 Mar 2021 19:29:59 +0100 |
This reverts commit 6e937ba7f8fb90d66cb3781f7fed32fb4239556a
This change breaks quickly at startup, as all interfaces in boards
are checked in vl.c in select_machine():
{
GSList *machines = object_class_get_list(TYPE_MACHINE, false);
}
In order to restrict v8M IDAU to TCG,
we need to first disable all incompatible boards when building
only KVM.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/cpu.c | 7 +++++++
target/arm/tcg/tcg-cpu-models.c | 8 --------
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 31f1b3df09..353cd652bc 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1510,9 +1510,16 @@ static const TypeInfo arm_cpu_type_info = {
.class_init = arm_cpu_class_init,
};
+static const TypeInfo idau_interface_type_info = {
+ .name = TYPE_IDAU_INTERFACE,
+ .parent = TYPE_INTERFACE,
+ .class_size = sizeof(IDAUInterfaceClass),
+};
+
static void arm_cpu_register_types(void)
{
type_register_static(&arm_cpu_type_info);
+ type_register_static(&idau_interface_type_info);
#ifdef CONFIG_KVM
type_register_static(&host_arm_cpu_type_info);
diff --git a/target/arm/tcg/tcg-cpu-models.c b/target/arm/tcg/tcg-cpu-models.c
index f4eea544b3..16ab5d5364 100644
--- a/target/arm/tcg/tcg-cpu-models.c
+++ b/target/arm/tcg/tcg-cpu-models.c
@@ -12,7 +12,6 @@
#include "tcg-cpu.h"
#include "internals.h"
-#include "target/arm/idau.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/boards.h"
#endif
@@ -987,17 +986,10 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
#endif
};
-static const TypeInfo idau_interface_type_info = {
- .name = TYPE_IDAU_INTERFACE,
- .parent = TYPE_INTERFACE,
- .class_size = sizeof(IDAUInterfaceClass),
-};
-
static void arm_tcg_cpu_register_types(void)
{
size_t i;
- type_register_static(&idau_interface_type_info);
for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
arm32_cpu_register(&arm_tcg_cpus[i]);
}
--
2.26.2
- [RFC v9 25/50] target/arm: cpu: fix style, (continued)
- [RFC v9 25/50] target/arm: cpu: fix style, Claudio Fontana, 2021/03/17
- [RFC v9 29/50] target/arm: cleanup cpu includes, Claudio Fontana, 2021/03/17
- [RFC v9 33/50] tests: do not run test-hmp on all machines for ARM KVM-only, Claudio Fontana, 2021/03/17
- [RFC v9 30/50] target/arm: remove broad "else" statements when checking accels, Claudio Fontana, 2021/03/17
- [RFC v9 34/50] tests: device-introspect-test: cope with ARM TCG-only devices, Claudio Fontana, 2021/03/17
- [RFC v9 22/50] target/arm: split a15 cpu model and 32bit class functions to cpu32.c, Claudio Fontana, 2021/03/17
- [RFC v9 09/50] target/arm: split cpregs from tcg/helper.c, Claudio Fontana, 2021/03/17
- [RFC v9 31/50] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM, Claudio Fontana, 2021/03/17
- [RFC v9 28/50] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/, Claudio Fontana, 2021/03/17
- [RFC v9 37/50] target/arm: create kvm cpu accel class, Claudio Fontana, 2021/03/17
- [RFC v9 36/50] Revert "target/arm: Restrict v8M IDAU to TCG",
Claudio Fontana <=
- [RFC v9 41/50] target/arm: add tcg cpu accel class, Claudio Fontana, 2021/03/17
- [RFC v9 44/50] target/arm: cpu-sve: split TCG and KVM functionality, Claudio Fontana, 2021/03/17
- [RFC v9 40/50] accel: add double dispatch mechanism for class initialization, Claudio Fontana, 2021/03/17
- [RFC v9 45/50] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64, Claudio Fontana, 2021/03/17
- [RFC v9 50/50] target/arm: refactor arm_cpu_finalize_features into cpu64, Claudio Fontana, 2021/03/17
- [RFC v9 39/50] accel: move call to accel_init_interfaces, Claudio Fontana, 2021/03/17
- [RFC v9 42/50] target/arm: move TCG gt timer creation code in tcg/, Claudio Fontana, 2021/03/17
- [RFC v9 48/50] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64, Claudio Fontana, 2021/03/17
- [RFC v9 47/50] target/arm: cpu-exceptions: new module, Claudio Fontana, 2021/03/17
- [RFC v9 24/50] target/arm: refactor exception and cpu code, Claudio Fontana, 2021/03/17