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[RFC v9 40/50] accel: add double dispatch mechanism for class initializa
From: |
Claudio Fontana |
Subject: |
[RFC v9 40/50] accel: add double dispatch mechanism for class initialization |
Date: |
Wed, 17 Mar 2021 19:30:03 +0100 |
while on x86 all CPU classes can use the same set of TCGCPUOps,
on ARM the right accel behavior depends on the type of the CPU.
So we need a way to specialize the accel behavior according to
the CPU. Therefore, add a second initialization, after the
accel_cpu->cpu_class_init, that allows to do this.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Cc: Paolo Bonzini <pbonzini@redhat.com>
---
include/hw/core/cpu.h | 6 ++++++
accel/accel-common.c | 12 ++++++++++++
target/i386/tcg/tcg-cpu.c | 8 +++++++-
3 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index c68bc3ba8a..d45f78290e 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -192,6 +192,12 @@ struct CPUClass {
/* when TCG is not available, this pointer is NULL */
struct TCGCPUOps *tcg_ops;
+
+ /*
+ * if not NULL, this is called in order for the CPUClass to initialize
+ * class data that depends on the accelerator, see accel/accel-common.c.
+ */
+ void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc);
};
/*
diff --git a/accel/accel-common.c b/accel/accel-common.c
index d77c09d7b5..2103397d5e 100644
--- a/accel/accel-common.c
+++ b/accel/accel-common.c
@@ -54,10 +54,22 @@ static void accel_init_cpu_int_aux(ObjectClass *klass, void
*opaque)
CPUClass *cc = CPU_CLASS(klass);
AccelCPUClass *accel_cpu = opaque;
+ /*
+ * double dispatch. The first callback allows the accel cpu
+ * to run initializations for the CPU,
+ * the second one allows the CPU to customize the accel cpu
+ * behavior according to the CPU.
+ *
+ * The second is currently only used by TCG, to specialize the
+ * TCGCPUOps depending on the CPU type.
+ */
cc->accel_cpu = accel_cpu;
if (accel_cpu->cpu_class_init) {
accel_cpu->cpu_class_init(cc);
}
+ if (cc->init_accel_cpu) {
+ cc->init_accel_cpu(accel_cpu, cc);
+ }
}
/* initialize the arch-specific accel CpuClass interfaces */
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index e311f52855..ba39531aa5 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -69,11 +69,17 @@ static struct TCGCPUOps x86_tcg_ops = {
#endif /* !CONFIG_USER_ONLY */
};
-static void tcg_cpu_class_init(CPUClass *cc)
+static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
{
+ /* for x86, all cpus use the same set of operations */
cc->tcg_ops = &x86_tcg_ops;
}
+static void tcg_cpu_class_init(CPUClass *cc)
+{
+ cc->init_accel_cpu = tcg_cpu_init_ops;
+}
+
/*
* TCG-specific defaults that override all CPU models when using TCG
*/
--
2.26.2
- [RFC v9 30/50] target/arm: remove broad "else" statements when checking accels, (continued)
- [RFC v9 30/50] target/arm: remove broad "else" statements when checking accels, Claudio Fontana, 2021/03/17
- [RFC v9 34/50] tests: device-introspect-test: cope with ARM TCG-only devices, Claudio Fontana, 2021/03/17
- [RFC v9 22/50] target/arm: split a15 cpu model and 32bit class functions to cpu32.c, Claudio Fontana, 2021/03/17
- [RFC v9 09/50] target/arm: split cpregs from tcg/helper.c, Claudio Fontana, 2021/03/17
- [RFC v9 31/50] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM, Claudio Fontana, 2021/03/17
- [RFC v9 28/50] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/, Claudio Fontana, 2021/03/17
- [RFC v9 37/50] target/arm: create kvm cpu accel class, Claudio Fontana, 2021/03/17
- [RFC v9 36/50] Revert "target/arm: Restrict v8M IDAU to TCG", Claudio Fontana, 2021/03/17
- [RFC v9 41/50] target/arm: add tcg cpu accel class, Claudio Fontana, 2021/03/17
- [RFC v9 44/50] target/arm: cpu-sve: split TCG and KVM functionality, Claudio Fontana, 2021/03/17
- [RFC v9 40/50] accel: add double dispatch mechanism for class initialization,
Claudio Fontana <=
- [RFC v9 45/50] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64, Claudio Fontana, 2021/03/17
- [RFC v9 50/50] target/arm: refactor arm_cpu_finalize_features into cpu64, Claudio Fontana, 2021/03/17
- [RFC v9 39/50] accel: move call to accel_init_interfaces, Claudio Fontana, 2021/03/17
- [RFC v9 42/50] target/arm: move TCG gt timer creation code in tcg/, Claudio Fontana, 2021/03/17
- [RFC v9 48/50] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64, Claudio Fontana, 2021/03/17
- [RFC v9 47/50] target/arm: cpu-exceptions: new module, Claudio Fontana, 2021/03/17
- [RFC v9 24/50] target/arm: refactor exception and cpu code, Claudio Fontana, 2021/03/17
- [RFC v9 49/50] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication, Claudio Fontana, 2021/03/17
- [RFC v9 46/50] target/arm: arch_dump: restrict ELFCLASS64 to AArch64, Claudio Fontana, 2021/03/17