[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC v9 42/50] target/arm: move TCG gt timer creation code in tcg/
From: |
Claudio Fontana |
Subject: |
[RFC v9 42/50] target/arm: move TCG gt timer creation code in tcg/ |
Date: |
Wed, 17 Mar 2021 19:30:05 +0100 |
we need to be careful not to use
if (tcg_enabled())
here, because of the VMSTATE definitions in machine.c,
which are only protected by CONFIG_TCG, and thus
it would break the --enable-tcg --enable-kvm build.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/tcg/tcg-cpu.h | 1 +
target/arm/cpu.c | 28 +++-------------------
target/arm/tcg/sysemu/tcg-cpu.c | 41 +++++++++++++++++++++++++++++++++
3 files changed, 45 insertions(+), 25 deletions(-)
diff --git a/target/arm/tcg/tcg-cpu.h b/target/arm/tcg/tcg-cpu.h
index dd08587949..3e4ce2c355 100644
--- a/target/arm/tcg/tcg-cpu.h
+++ b/target/arm/tcg/tcg-cpu.h
@@ -33,6 +33,7 @@ void tcg_arm_init_accel_cpu(AccelCPUClass *accel_cpu,
CPUClass *cc);
/* Do semihosting call and set the appropriate return value. */
void tcg_handle_semihosting(CPUState *cs);
bool tcg_cpu_realizefn(CPUState *cs, Error **errp);
+bool tcg_cpu_realize_gt_timers(CPUState *cs, Error **errp);
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 09c1db604a..b2ca705f71 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -870,32 +870,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
bool no_aa32 = false;
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
- {
- uint64_t scale;
-
- if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
- if (!cpu->gt_cntfrq_hz) {
- error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
- cpu->gt_cntfrq_hz);
- return;
- }
- scale = gt_cntfrq_period_ns(cpu);
- } else {
- scale = GTIMER_SCALE;
- }
-
- cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
- arm_gt_ptimer_cb, cpu);
- cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
- arm_gt_vtimer_cb, cpu);
- cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
- arm_gt_htimer_cb, cpu);
- cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
- arm_gt_stimer_cb, cpu);
- cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
- arm_gt_hvtimer_cb, cpu);
+ if (!tcg_cpu_realize_gt_timers(cs, errp)) {
+ return;
}
-#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
+#endif
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
diff --git a/target/arm/tcg/sysemu/tcg-cpu.c b/target/arm/tcg/sysemu/tcg-cpu.c
index 115ac523dc..777eb948df 100644
--- a/target/arm/tcg/sysemu/tcg-cpu.c
+++ b/target/arm/tcg/sysemu/tcg-cpu.c
@@ -54,6 +54,46 @@ void tcg_handle_semihosting(CPUState *cs)
}
}
+/*
+ * we cannot use tcg_enabled() to condition the call to this function,
+ * due to the fields VMSTATE definitions in machine.c : it would break
+ * the --enable-tcg --enable-kvm build. We need to run this code whenever
+ * CONFIG_TCG is true, regardless of the chosen accelerator.
+ *
+ * So we cannot call this from tcg_cpu_realizefn, as this needs to
+ * be called whenever TCG is built-in, regardless of whether it is
+ * enabled or not.
+ */
+bool tcg_cpu_realize_gt_timers(CPUState *cs, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ uint64_t scale;
+
+ if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
+ if (!cpu->gt_cntfrq_hz) {
+ error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
+ cpu->gt_cntfrq_hz);
+ return false;
+ }
+ scale = gt_cntfrq_period_ns(cpu);
+ } else {
+ scale = GTIMER_SCALE;
+ }
+
+ cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
+ arm_gt_ptimer_cb, cpu);
+ cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
+ arm_gt_vtimer_cb, cpu);
+ cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
+ arm_gt_htimer_cb, cpu);
+ cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
+ arm_gt_stimer_cb, cpu);
+ cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
+ arm_gt_hvtimer_cb, cpu);
+ return true;
+}
+
bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
{
ARMCPU *cpu = ARM_CPU(cs);
@@ -75,5 +115,6 @@ bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
return false;
}
}
+
return true;
}
--
2.26.2
- [RFC v9 31/50] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM, (continued)
- [RFC v9 31/50] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM, Claudio Fontana, 2021/03/17
- [RFC v9 28/50] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/, Claudio Fontana, 2021/03/17
- [RFC v9 37/50] target/arm: create kvm cpu accel class, Claudio Fontana, 2021/03/17
- [RFC v9 36/50] Revert "target/arm: Restrict v8M IDAU to TCG", Claudio Fontana, 2021/03/17
- [RFC v9 41/50] target/arm: add tcg cpu accel class, Claudio Fontana, 2021/03/17
- [RFC v9 44/50] target/arm: cpu-sve: split TCG and KVM functionality, Claudio Fontana, 2021/03/17
- [RFC v9 40/50] accel: add double dispatch mechanism for class initialization, Claudio Fontana, 2021/03/17
- [RFC v9 45/50] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64, Claudio Fontana, 2021/03/17
- [RFC v9 50/50] target/arm: refactor arm_cpu_finalize_features into cpu64, Claudio Fontana, 2021/03/17
- [RFC v9 39/50] accel: move call to accel_init_interfaces, Claudio Fontana, 2021/03/17
- [RFC v9 42/50] target/arm: move TCG gt timer creation code in tcg/,
Claudio Fontana <=
- [RFC v9 48/50] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64, Claudio Fontana, 2021/03/17
- [RFC v9 47/50] target/arm: cpu-exceptions: new module, Claudio Fontana, 2021/03/17
- [RFC v9 24/50] target/arm: refactor exception and cpu code, Claudio Fontana, 2021/03/17
- [RFC v9 49/50] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication, Claudio Fontana, 2021/03/17
- [RFC v9 46/50] target/arm: arch_dump: restrict ELFCLASS64 to AArch64, Claudio Fontana, 2021/03/17