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[PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs
From: |
Alistair Francis |
Subject: |
[PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs |
Date: |
Thu, 17 Dec 2020 22:00:58 -0800 |
Currently the riscv_is_32_bit() function only supports the generic rv32
CPUs. Extend the function to support the SiFive and LowRISC CPUs as
well.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id:
9a13764115ba78688ba61b56526c6de65fc3ef42.1608142916.git.alistair.francis@wdc.com
---
hw/riscv/boot.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index d62f3dc758..3c70ac75d7 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -41,7 +41,17 @@
bool riscv_is_32_bit(MachineState *machine)
{
- if (!strncmp(machine->cpu_type, "rv32", 4)) {
+ /*
+ * To determine if the CPU is 32-bit we need to check a few different CPUs.
+ *
+ * If the CPU starts with rv32
+ * If the CPU is a sifive 3 seriries CPU (E31, U34)
+ * If it's the Ibex CPU
+ */
+ if (!strncmp(machine->cpu_type, "rv32", 4) ||
+ (!strncmp(machine->cpu_type, "sifive", 6) &&
+ machine->cpu_type[8] == '3') ||
+ !strncmp(machine->cpu_type, "lowrisc-ibex", 12)) {
return true;
} else {
return false;
--
2.29.2
- [PULL 00/23] riscv-to-apply queue, Alistair Francis, 2020/12/18
- [PULL 01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB, Alistair Francis, 2020/12/18
- [PULL 02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash, Alistair Francis, 2020/12/18
- [PULL 04/23] target/riscv: Fix the bug of HLVX/HLV/HSV, Alistair Francis, 2020/12/18
- [PULL 05/23] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR, Alistair Francis, 2020/12/18
- [PULL 03/23] hw/core/register.c: Don't use '#' flag of printf format, Alistair Francis, 2020/12/18
- [PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs,
Alistair Francis <=
- [PULL 08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU, Alistair Francis, 2020/12/18
- [PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim process, Alistair Francis, 2020/12/18
- [PULL 09/23] riscv: spike: Remove target macro conditionals, Alistair Francis, 2020/12/18
- [PULL 10/23] riscv: virt: Remove target macro conditionals, Alistair Francis, 2020/12/18
- [PULL 11/23] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 12/23] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 14/23] hw/riscv: sifive_u: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 15/23] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/12/18
- [PULL 13/23] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function, Alistair Francis, 2020/12/18