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[PULL 16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function
From: |
Alistair Francis |
Subject: |
[PULL 16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function |
Date: |
Thu, 17 Dec 2020 22:01:07 -0800 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id:
ebd37b237a8cbe457335b948bd57f487b6b31869.1608142916.git.alistair.francis@wdc.com
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu.c | 9 +++++++++
2 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9c064f3094..6339e84819 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -384,6 +384,8 @@ FIELD(TB_FLAGS, VILL, 8, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 9, 1)
+bool riscv_cpu_is_32bit(CPURISCVState *env);
+
/*
* A simplification for VLMAX
* = (1 << LMUL) * VLEN / (8 * (1 << SEW))
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6a0264fc6b..32a6916b8a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -108,6 +108,15 @@ const char *riscv_cpu_get_trap_name(target_ulong cause,
bool async)
}
}
+bool riscv_cpu_is_32bit(CPURISCVState *env)
+{
+ if (env->misa & RV64) {
+ return false;
+ }
+
+ return true;
+}
+
static void set_misa(CPURISCVState *env, target_ulong misa)
{
env->misa_mask = env->misa = misa;
--
2.29.2
- [PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs, (continued)
- [PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs, Alistair Francis, 2020/12/18
- [PULL 08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU, Alistair Francis, 2020/12/18
- [PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim process, Alistair Francis, 2020/12/18
- [PULL 09/23] riscv: spike: Remove target macro conditionals, Alistair Francis, 2020/12/18
- [PULL 10/23] riscv: virt: Remove target macro conditionals, Alistair Francis, 2020/12/18
- [PULL 11/23] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 12/23] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 14/23] hw/riscv: sifive_u: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 15/23] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/12/18
- [PULL 13/23] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function,
Alistair Francis <=
- [PULL 18/23] target/riscv: cpu: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 17/23] target/riscv: Specify the XLEN for CPUs, Alistair Francis, 2020/12/18
- [PULL 20/23] target/riscv: csr: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 19/23] target/riscv: cpu_helper: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 21/23] target/riscv: cpu: Set XLEN independently from target, Alistair Francis, 2020/12/18
- [PULL 22/23] hw/riscv: Use the CPU to determine if 32-bit, Alistair Francis, 2020/12/18
- [PULL 23/23] riscv/opentitan: Update the OpenTitan memory layout, Alistair Francis, 2020/12/18
- Re: [PULL 00/23] riscv-to-apply queue, Peter Maydell, 2020/12/18