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[PULL 03/23] hw/core/register.c: Don't use '#' flag of printf format
From: |
Alistair Francis |
Subject: |
[PULL 03/23] hw/core/register.c: Don't use '#' flag of printf format |
Date: |
Thu, 17 Dec 2020 22:00:54 -0800 |
From: Xinhao Zhang <zhangxinhao1@huawei.com>
Fix code style. Don't use '#' flag of printf format ('%#') in
format strings, use '0x' prefix instead
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
Signed-off-by: Kai Deng <dengkai1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201116140148.2850128-1-zhangxinhao1@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/core/register.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/core/register.c b/hw/core/register.c
index 3600ef5bde..d6f8c20816 100644
--- a/hw/core/register.c
+++ b/hw/core/register.c
@@ -80,7 +80,7 @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t
we,
if (!ac || !ac->name) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: write to undefined device state "
- "(written value: %#" PRIx64 ")\n", prefix, val);
+ "(written value: 0x%" PRIx64 ")\n", prefix, val);
return;
}
@@ -89,14 +89,14 @@ void register_write(RegisterInfo *reg, uint64_t val,
uint64_t we,
test = (old_val ^ val) & ac->rsvd;
if (test) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: change of value in reserved bit"
- "fields: %#" PRIx64 ")\n", prefix, test);
+ "fields: 0x%" PRIx64 ")\n", prefix, test);
}
test = val & ac->unimp;
if (test) {
qemu_log_mask(LOG_UNIMP,
- "%s:%s writing %#" PRIx64 " to unimplemented bits:" \
- " %#" PRIx64 "\n",
+ "%s:%s writing 0x%" PRIx64 " to unimplemented bits:" \
+ " 0x%" PRIx64 "\n",
prefix, reg->access->name, val, ac->unimp);
}
@@ -112,7 +112,7 @@ void register_write(RegisterInfo *reg, uint64_t val,
uint64_t we,
}
if (debug) {
- qemu_log("%s:%s: write of value %#" PRIx64 "\n", prefix, ac->name,
+ qemu_log("%s:%s: write of value 0x%" PRIx64 "\n", prefix, ac->name,
new_val);
}
@@ -150,7 +150,7 @@ uint64_t register_read(RegisterInfo *reg, uint64_t re,
const char* prefix,
}
if (debug) {
- qemu_log("%s:%s: read of value %#" PRIx64 "\n", prefix,
+ qemu_log("%s:%s: read of value 0x%" PRIx64 "\n", prefix,
ac->name, ret);
}
@@ -193,7 +193,7 @@ void register_write_memory(void *opaque, hwaddr addr,
if (!reg) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: write to unimplemented register " \
- "at address: %#" PRIx64 "\n", reg_array->prefix, addr);
+ "at address: 0x%" PRIx64 "\n", reg_array->prefix, addr);
return;
}
@@ -222,7 +222,7 @@ uint64_t register_read_memory(void *opaque, hwaddr addr,
if (!reg) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: read to unimplemented register " \
- "at address: %#" PRIx64 "\n", reg_array->prefix, addr);
+ "at address: 0x%" PRIx64 "\n", reg_array->prefix, addr);
return 0;
}
--
2.29.2
- [PULL 00/23] riscv-to-apply queue, Alistair Francis, 2020/12/18
- [PULL 01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB, Alistair Francis, 2020/12/18
- [PULL 02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash, Alistair Francis, 2020/12/18
- [PULL 04/23] target/riscv: Fix the bug of HLVX/HLV/HSV, Alistair Francis, 2020/12/18
- [PULL 05/23] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR, Alistair Francis, 2020/12/18
- [PULL 03/23] hw/core/register.c: Don't use '#' flag of printf format,
Alistair Francis <=
- [PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs, Alistair Francis, 2020/12/18
- [PULL 08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU, Alistair Francis, 2020/12/18
- [PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim process, Alistair Francis, 2020/12/18
- [PULL 09/23] riscv: spike: Remove target macro conditionals, Alistair Francis, 2020/12/18
- [PULL 10/23] riscv: virt: Remove target macro conditionals, Alistair Francis, 2020/12/18
- [PULL 11/23] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 12/23] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 14/23] hw/riscv: sifive_u: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 15/23] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/12/18
- [PULL 13/23] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/12/18