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[PULL 00/23] riscv-to-apply queue
From: |
Alistair Francis |
Subject: |
[PULL 00/23] riscv-to-apply queue |
Date: |
Thu, 17 Dec 2020 22:00:51 -0800 |
The following changes since commit 75ee62ac606bfc9eb59310b9446df3434bf6e8c2:
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request'
into staging (2020-12-17 18:53:36 +0000)
are available in the Git repository at:
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201217-1
for you to fetch changes up to d31e970a01e7399b9cd43ec0dc00c857d968987e:
riscv/opentitan: Update the OpenTitan memory layout (2020-12-17 21:56:44
-0800)
----------------------------------------------------------------
A collection of RISC-V improvements:
- Improve the sifive_u DTB generation
- Add QSPI NOR flash to Microchip PFSoC
- Fix a bug in the Hypervisor HLVX/HLV/HSV instructions
- Fix some mstatus mask defines
- Ibex PLIC improvements
- OpenTitan memory layout update
- Initial steps towards support for 32-bit CPUs on 64-bit builds
----------------------------------------------------------------
Alex Richardson (1):
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
Alistair Francis (18):
intc/ibex_plic: Clear interrupts that occur during claim process
hw/riscv: Expand the is 32-bit check to support more CPUs
target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
riscv: spike: Remove target macro conditionals
riscv: virt: Remove target macro conditionals
hw/riscv: boot: Remove compile time XLEN checks
hw/riscv: virt: Remove compile time XLEN checks
hw/riscv: spike: Remove compile time XLEN checks
hw/riscv: sifive_u: Remove compile time XLEN checks
target/riscv: fpu_helper: Match function defs in HELPER macros
target/riscv: Add a riscv_cpu_is_32bit() helper function
target/riscv: Specify the XLEN for CPUs
target/riscv: cpu: Remove compile time XLEN checks
target/riscv: cpu_helper: Remove compile time XLEN checks
target/riscv: csr: Remove compile time XLEN checks
target/riscv: cpu: Set XLEN independently from target
hw/riscv: Use the CPU to determine if 32-bit
riscv/opentitan: Update the OpenTitan memory layout
Anup Patel (1):
hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
Vitaly Wool (1):
hw/riscv: microchip_pfsoc: add QSPI NOR flash
Xinhao Zhang (1):
hw/core/register.c: Don't use '#' flag of printf format
Yifei Jiang (1):
target/riscv: Fix the bug of HLVX/HLV/HSV
include/hw/riscv/boot.h | 14 +--
include/hw/riscv/microchip_pfsoc.h | 3 +
include/hw/riscv/opentitan.h | 23 +++--
include/hw/riscv/spike.h | 6 --
include/hw/riscv/virt.h | 6 --
target/riscv/cpu.h | 8 ++
target/riscv/cpu_bits.h | 8 +-
target/riscv/helper.h | 24 ++---
hw/core/register.c | 16 ++--
hw/intc/ibex_plic.c | 13 ++-
hw/riscv/boot.c | 70 ++++++++-------
hw/riscv/microchip_pfsoc.c | 21 +++++
hw/riscv/opentitan.c | 81 ++++++++++++-----
hw/riscv/sifive_u.c | 74 ++++++++++------
hw/riscv/spike.c | 52 ++++++-----
hw/riscv/virt.c | 39 ++++----
target/riscv/cpu.c | 84 ++++++++++++------
target/riscv/cpu_helper.c | 15 ++--
target/riscv/csr.c | 176 +++++++++++++++++++------------------
target/riscv/fpu_helper.c | 8 --
20 files changed, 434 insertions(+), 307 deletions(-)
- [PULL 00/23] riscv-to-apply queue,
Alistair Francis <=
- [PULL 01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB, Alistair Francis, 2020/12/18
- [PULL 02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash, Alistair Francis, 2020/12/18
- [PULL 04/23] target/riscv: Fix the bug of HLVX/HLV/HSV, Alistair Francis, 2020/12/18
- [PULL 05/23] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR, Alistair Francis, 2020/12/18
- [PULL 03/23] hw/core/register.c: Don't use '#' flag of printf format, Alistair Francis, 2020/12/18
- [PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs, Alistair Francis, 2020/12/18
- [PULL 08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU, Alistair Francis, 2020/12/18
- [PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim process, Alistair Francis, 2020/12/18
- [PULL 09/23] riscv: spike: Remove target macro conditionals, Alistair Francis, 2020/12/18
- [PULL 10/23] riscv: virt: Remove target macro conditionals, Alistair Francis, 2020/12/18