Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU

[Philippe Mathieu-Daudé]

> On 9/15/18 11:50 AM, Fredrik Noring wrote:
[...]
>> +    {
>> +        .name = "R5900",
> 
> What bothers me here is you are not modeling "The" unique R5900, but a
> cpu which implements the R5900 architecture.
> 
> From the "TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)":
> 
>   The TX7901 MIPS RISC microcontroller is a highly integrated solution
>   based on Toshiba’s dual-issue super-scalar pipeline Processor Core,
>   the C790 (henceforth referred to as “the C790”).
> 
>   C790 High-performance MIPS CPU Core on which the TX7901 is based.
> 
> So the correct core name is "C790".

FYI, if the qemu-system mode is ever implemented, the TMPR7901 is the
SoC that uses the C790 core:
https://www.toshiba.co.jp/about/press/2001_09/pr2701.htm

"The core of the new reduced instruction set computer (RISC)
microprocessor, the TX79 family, was developed by ArTile Microsystems,
Inc., a fully-owned subsidiary of Toshiba America Electronic Components,
Inc. The core of the processor is based on know-how cultivated in the
joint-development with Sony Computer Entertainment Inc. of
EmotionEngine(R), the processor used in PlayStation(R)2. "

Also:
https://www.design-reuse.com/news/405/artile-thinks-entertainment-soc.html

"ArTile Microsystems has announced the first in a family of MIPS-based
high-performance systems-on-chip (SOCs). The TMPR7901B incorporates a
multimedia-enhanced RISC processor core with instruction and data cache
memories, PCI and Ethernet interfaces, timers, and memory controllers in
a single device. [...]

The 790X family starts with the C790, a 128-bit MIPS-compatible RISC
processor core with multiply-accumulate and bit-manipulation instruction
enhancements. On the TMPR7901B device, the core comes with dual
32-kbyte, 2-way set-associative caches for instruction and data on chip
and a 1Gbyte SDRAM memory controller with DMA access for high-speed
external memory access.

The device also has a dual 10/100 Mbps Ethernet MAC, two separate PCI
controllers (33 MHz and 66 MHz), and three 24-bit timer-counters. The
presence of the PCI bus bridges on-chip solves a system bottleneck that
has compromised the performance of other, two-chip solutions. A dual
UART and a 16-line interrupt controller complete the TMPR7901's bundle."

TX7901 User’s Manual:

https://www.datasheetarchive.com/TMPR7901-datasheet.html