Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU

[Maciej W. Rozycki]

On Tue, 25 Sep 2018, Philippe Mathieu-Daudé wrote:

> >>>> >From the DS:
> >>>>
> >>>>   The C790 core has the following features:
> >>>>    - Large on-chip caches
> >>>>     • Instruction cache: 32KB, 2-way set associative
> >>>>     • Data cache: 32KB, 2-way set-associative (with write-back protocol)
> >>>>
> >>>> 0x2 << CP0C0_K0 is 'Uncached', why you selected this and not 0x3 for
> >>>> 'Cacheable, write-back, write allocate'?
> >>>
> >>>  No other MIPS emulation does what you suggest, which is why I refrained 
> >>> from commenting on the K0 field and commented on the ICE/DCE bits only.  
> >>> See:
> >>>
> >>> /* Have config1, uncached coherency */
> >>> #define MIPS_CONFIG0                                              \
> >>>   ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
> >>>
> >>> elsewhere in this file.
> >>
> >> Yes, this was just out of curiosity.
> 
> Maciej, FYI I now remembered the thread that triggered this curiosity:
> 
> http://lists.nongnu.org/archive/html/qemu-devel/2018-08/msg03796.html

 Thanks for the pointer; I'm not subscribed to the QEMU mailing list these 
days anymore.

 For the record, you can achieve the same effect by using the TLB and the 
cache mode of the page(s) mapped, possibly with a wired entry, rather than 
with the physical kernel segments (KSEG0/KSEG1/XKPHYS).

 There's also SPRAM that uses the cache interface in some implementations 
(MTI 4K and M4K cores if memory serves; possibly other ones as well), that 
you may want to model in QEMU one day too.

  Maciej