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Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU |
Date: |
Tue, 25 Sep 2018 12:46:13 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 |
On 9/25/18 10:25 AM, Maciej W. Rozycki wrote:
> On Mon, 24 Sep 2018, Philippe Mathieu-Daudé wrote:
>>>> >From the DS:
>>>>
>>>> The C790 core has the following features:
>>>> - Large on-chip caches
>>>> • Instruction cache: 32KB, 2-way set associative
>>>> • Data cache: 32KB, 2-way set-associative (with write-back protocol)
>>>>
>>>> 0x2 << CP0C0_K0 is 'Uncached', why you selected this and not 0x3 for
>>>> 'Cacheable, write-back, write allocate'?
>>>
>>> No other MIPS emulation does what you suggest, which is why I refrained
>>> from commenting on the K0 field and commented on the ICE/DCE bits only.
>>> See:
>>>
>>> /* Have config1, uncached coherency */
>>> #define MIPS_CONFIG0 \
>>> ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
>>>
>>> elsewhere in this file.
>>
>> Yes, this was just out of curiosity.
Maciej, FYI I now remembered the thread that triggered this curiosity:
http://lists.nongnu.org/archive/html/qemu-devel/2018-08/msg03796.html
> Also the value of this field at reset is undefined for this CPU (as is
> architecturally, though some implementations might work otherwise), so 0x2
> is as good as any. For the user emulation mode we could consider choosing
> what the kernel would use, however that would only matter if we had the
> cache properly emulated.
- Re: [Qemu-devel] [PATCH v5 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, (continued)
[Qemu-devel] [PATCH v5 3/8] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV, Fredrik Noring, 2018/09/19
[Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Fredrik Noring, 2018/09/19
- Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Philippe Mathieu-Daudé, 2018/09/20
- Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Philippe Mathieu-Daudé, 2018/09/20
- Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Maciej W. Rozycki, 2018/09/20
- Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Philippe Mathieu-Daudé, 2018/09/24
- Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Maciej W. Rozycki, 2018/09/25
- Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU,
Philippe Mathieu-Daudé <=
- Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Maciej W. Rozycki, 2018/09/25
Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Fredrik Noring, 2018/09/27
Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Philippe Mathieu-Daudé, 2018/09/28
Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Jürgen Urban, 2018/09/25
Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Fredrik Noring, 2018/09/26
Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU, Philippe Mathieu-Daudé, 2018/09/24
[Qemu-devel] [PATCH v5 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, Fredrik Noring, 2018/09/19
[Qemu-devel] [PATCH v5 7/8] linux-user/mips: Recognise the R5900 CPU model, Fredrik Noring, 2018/09/19
[Qemu-devel] [PATCH v5 8/8] elf: Toshiba/Sony rather than MIPS are the implementors of the R5900, Fredrik Noring, 2018/09/19
Re: [Qemu-devel] [PATCH v5 0/8] target/mips: Support R5900 GCC programs in user mode, Aleksandar Markovic, 2018/09/20