[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 06/25] target/openrisc: Fix singlestep_enabled
From: |
Stafford Horne |
Subject: |
[Qemu-devel] [PULL 06/25] target/openrisc: Fix singlestep_enabled |
Date: |
Mon, 2 Jul 2018 22:57:47 +0900 |
From: Richard Henderson <address@hidden>
We failed to store to cpu_pc before raising the exception,
which caused us to re-execute the same insn that we stepped.
Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>
---
target/openrisc/translate.c | 35 +++++++++++++++++------------------
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 43bdf378eb..22848b17ad 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1335,31 +1335,30 @@ static void openrisc_tr_tb_stop(DisasContextBase
*dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
+ /* If we have already exited the TB, nothing following has effect. */
+ if (dc->base.is_jmp == DISAS_NORETURN) {
+ return;
+ }
+
if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) {
tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0);
}
tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4);
- if (dc->base.is_jmp == DISAS_NEXT) {
- dc->base.is_jmp = DISAS_UPDATE;
- tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
- }
- if (unlikely(dc->base.singlestep_enabled)) {
- gen_exception(dc, EXCP_DEBUG);
- } else {
- switch (dc->base.is_jmp) {
- case DISAS_TOO_MANY:
- gen_goto_tb(dc, 0, dc->base.pc_next);
- break;
- case DISAS_NORETURN:
- break;
- case DISAS_UPDATE:
- case DISAS_EXIT:
+ switch (dc->base.is_jmp) {
+ case DISAS_TOO_MANY:
+ gen_goto_tb(dc, 0, dc->base.pc_next);
+ break;
+ case DISAS_UPDATE:
+ case DISAS_EXIT:
+ if (unlikely(dc->base.singlestep_enabled)) {
+ gen_exception(dc, EXCP_DEBUG);
+ } else {
tcg_gen_exit_tb(NULL, 0);
- break;
- default:
- g_assert_not_reached();
}
+ break;
+ default:
+ g_assert_not_reached();
}
}
--
2.17.0
- [Qemu-devel] [PULL 00/25] OpenRISC updates for 3.0, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 01/25] target/openrisc: Fix mtspr shadow gprs, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 03/25] target/openrisc: Log interrupts, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 05/25] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 04/25] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 02/25] target/openrisc: Add print_insn_or1k, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 06/25] target/openrisc: Fix singlestep_enabled,
Stafford Horne <=
- [Qemu-devel] [PULL 07/25] target/openrisc: Link more translation blocks, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 09/25] target/openrisc: Exit the TB after l.mtspr, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 10/25] target/openrisc: Form the spr index from tcg, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 11/25] target/openrisc: Merge tlb allocation into CPUOpenRISCState, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 12/25] target/openrisc: Remove indirect function calls for mmu, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 13/25] target/openrisc: Merge mmu_helper.c into mmu.c, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 14/25] target/openrisc: Reduce tlb to a single dimension, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 15/25] target/openrisc: Fix tlb flushing in mtspr, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 16/25] target/openrisc: Fix cpu_mmu_index, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 17/25] target/openrisc: Use identical sizes for ITLB and DTLB, Stafford Horne, 2018/07/02