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[Qemu-devel] [PULL 01/25] target/openrisc: Fix mtspr shadow gprs
From: |
Stafford Horne |
Subject: |
[Qemu-devel] [PULL 01/25] target/openrisc: Fix mtspr shadow gprs |
Date: |
Mon, 2 Jul 2018 22:57:42 +0900 |
From: Richard Henderson <address@hidden>
Missing break when this feature was added in 89e71e873d
("target/openrisc: implement shadow registers"). This was causing
strange issues as we get writes into the translation block jump cache
and other bits of state.
Fixes: 89e71e873d ("target/openrisc: implement shadow registers")
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>
---
target/openrisc/sys_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index b284064381..2f337363ec 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -98,6 +98,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
idx = (spr - 1024);
env->shadow_gpr[idx / 32][idx % 32] = rb;
+ break;
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
--
2.17.0
- [Qemu-devel] [PULL 00/25] OpenRISC updates for 3.0, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 01/25] target/openrisc: Fix mtspr shadow gprs,
Stafford Horne <=
- [Qemu-devel] [PULL 03/25] target/openrisc: Log interrupts, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 05/25] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 04/25] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 02/25] target/openrisc: Add print_insn_or1k, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 06/25] target/openrisc: Fix singlestep_enabled, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 07/25] target/openrisc: Link more translation blocks, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 09/25] target/openrisc: Exit the TB after l.mtspr, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 10/25] target/openrisc: Form the spr index from tcg, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 11/25] target/openrisc: Merge tlb allocation into CPUOpenRISCState, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 12/25] target/openrisc: Remove indirect function calls for mmu, Stafford Horne, 2018/07/02