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[Qemu-devel] [PULL 03/25] target/openrisc: Log interrupts
From: |
Stafford Horne |
Subject: |
[Qemu-devel] [PULL 03/25] target/openrisc: Log interrupts |
Date: |
Mon, 2 Jul 2018 22:57:44 +0900 |
From: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>
---
target/openrisc/interrupt.c | 30 +++++++++++++++++++++++++-----
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 3959671c59..25351d5de3 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -32,6 +32,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUOpenRISCState *env = &cpu->env;
+ int exception = cs->exception_index;
env->epcr = env->pc;
if (env->dflag) {
@@ -41,12 +42,12 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
} else {
env->sr &= ~SR_DSX;
}
- if (cs->exception_index == EXCP_SYSCALL) {
+ if (exception == EXCP_SYSCALL) {
env->epcr += 4;
}
/* When we have an illegal instruction the error effective address
shall be set to the illegal instruction address. */
- if (cs->exception_index == EXCP_ILLEGAL) {
+ if (exception == EXCP_ILLEGAL) {
env->eear = env->pc;
}
@@ -66,8 +67,27 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
env->lock_addr = -1;
- if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {
- hwaddr vect_pc = cs->exception_index << 8;
+ if (exception > 0 && exception < EXCP_NR) {
+ static const char * const int_name[EXCP_NR] = {
+ [EXCP_RESET] = "RESET",
+ [EXCP_BUSERR] = "BUSERR (bus error)",
+ [EXCP_DPF] = "DFP (data protection fault)",
+ [EXCP_IPF] = "IPF (code protection fault)",
+ [EXCP_TICK] = "TICK (timer interrupt)",
+ [EXCP_ALIGN] = "ALIGN",
+ [EXCP_ILLEGAL] = "ILLEGAL",
+ [EXCP_INT] = "INT (device interrupt)",
+ [EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)",
+ [EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)",
+ [EXCP_RANGE] = "RANGE",
+ [EXCP_SYSCALL] = "SYSCALL",
+ [EXCP_FPE] = "FPE",
+ [EXCP_TRAP] = "TRAP",
+ };
+
+ qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]);
+
+ hwaddr vect_pc = exception << 8;
if (env->cpucfgr & CPUCFGR_EVBARP) {
vect_pc |= env->evbar;
}
@@ -76,7 +96,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
}
env->pc = vect_pc;
} else {
- cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
+ cpu_abort(cs, "Unhandled exception 0x%x\n", exception);
}
#endif
--
2.17.0
- [Qemu-devel] [PULL 00/25] OpenRISC updates for 3.0, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 01/25] target/openrisc: Fix mtspr shadow gprs, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 03/25] target/openrisc: Log interrupts,
Stafford Horne <=
- [Qemu-devel] [PULL 05/25] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 04/25] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 02/25] target/openrisc: Add print_insn_or1k, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 06/25] target/openrisc: Fix singlestep_enabled, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 07/25] target/openrisc: Link more translation blocks, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 09/25] target/openrisc: Exit the TB after l.mtspr, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 10/25] target/openrisc: Form the spr index from tcg, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 11/25] target/openrisc: Merge tlb allocation into CPUOpenRISCState, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 12/25] target/openrisc: Remove indirect function calls for mmu, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 13/25] target/openrisc: Merge mmu_helper.c into mmu.c, Stafford Horne, 2018/07/02