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[Qemu-devel] [PULL 13/25] target/openrisc: Merge mmu_helper.c into mmu.c
From: |
Stafford Horne |
Subject: |
[Qemu-devel] [PULL 13/25] target/openrisc: Merge mmu_helper.c into mmu.c |
Date: |
Mon, 2 Jul 2018 22:57:54 +0900 |
From: Richard Henderson <address@hidden>
With tlb_fill in mmu.c, we can simplify things further.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>
---
target/openrisc/Makefile.objs | 2 +-
target/openrisc/mmu.c | 11 ++++++++++
target/openrisc/mmu_helper.c | 40 -----------------------------------
3 files changed, 12 insertions(+), 41 deletions(-)
delete mode 100644 target/openrisc/mmu_helper.c
diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs
index 8b8a890c59..b5432f4684 100644
--- a/target/openrisc/Makefile.objs
+++ b/target/openrisc/Makefile.objs
@@ -1,7 +1,7 @@
obj-$(CONFIG_SOFTMMU) += machine.o
obj-y += cpu.o exception.o interrupt.o mmu.o translate.o disas.o
obj-y += exception_helper.o fpu_helper.o \
- interrupt_helper.o mmu_helper.o sys_helper.o
+ interrupt_helper.o sys_helper.o
obj-y += gdbstub.o
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index b2effaa6d7..9b4b5cf04f 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -240,4 +240,15 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs,
vaddr addr)
return phys_addr;
}
}
+
+void tlb_fill(CPUState *cs, target_ulong addr, int size,
+ MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
+{
+ int ret = openrisc_cpu_handle_mmu_fault(cs, addr, size,
+ access_type, mmu_idx);
+ if (ret) {
+ /* Raise Exception. */
+ cpu_loop_exit_restore(cs, retaddr);
+ }
+}
#endif
diff --git a/target/openrisc/mmu_helper.c b/target/openrisc/mmu_helper.c
deleted file mode 100644
index 97e1d17b5a..0000000000
--- a/target/openrisc/mmu_helper.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * OpenRISC MMU helper routines
- *
- * Copyright (c) 2011-2012 Jia Liu <address@hidden>
- * Zhizhou Zhang <address@hidden>
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "qemu/osdep.h"
-#include "cpu.h"
-#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
-
-#ifndef CONFIG_USER_ONLY
-
-void tlb_fill(CPUState *cs, target_ulong addr, int size,
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
-{
- int ret;
-
- ret = openrisc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
-
- if (ret) {
- /* Raise Exception. */
- cpu_loop_exit_restore(cs, retaddr);
- }
-}
-#endif
--
2.17.0
- [Qemu-devel] [PULL 03/25] target/openrisc: Log interrupts, (continued)
- [Qemu-devel] [PULL 03/25] target/openrisc: Log interrupts, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 05/25] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 04/25] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 02/25] target/openrisc: Add print_insn_or1k, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 06/25] target/openrisc: Fix singlestep_enabled, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 07/25] target/openrisc: Link more translation blocks, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 09/25] target/openrisc: Exit the TB after l.mtspr, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 10/25] target/openrisc: Form the spr index from tcg, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 11/25] target/openrisc: Merge tlb allocation into CPUOpenRISCState, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 12/25] target/openrisc: Remove indirect function calls for mmu, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 13/25] target/openrisc: Merge mmu_helper.c into mmu.c,
Stafford Horne <=
- [Qemu-devel] [PULL 14/25] target/openrisc: Reduce tlb to a single dimension, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 15/25] target/openrisc: Fix tlb flushing in mtspr, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 16/25] target/openrisc: Fix cpu_mmu_index, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 17/25] target/openrisc: Use identical sizes for ITLB and DTLB, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 18/25] target/openrisc: Stub out handle_mmu_fault for softmmu, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 19/25] target/openrisc: Increase the TLB size, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 20/25] target/openrisc: Reorg tlb lookup, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 21/25] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 23/25] linux-user: Fix struct sigaltstack for openrisc, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 22/25] linux-user: Implement signals for openrisc, Stafford Horne, 2018/07/02