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[Qemu-devel] [PULL 21/26] ppc: POWER7 had ACOP and PID registers
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 21/26] ppc: POWER7 had ACOP and PID registers |
Date: |
Tue, 7 Jun 2016 20:48:08 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
We only had them on POWER8, add them to POWER7 as well
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate_init.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 55f8553..ad6f2f3 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8024,6 +8024,21 @@ static void gen_spr_power8_book4(CPUPPCState *env)
#endif
}
+static void gen_spr_power7_book4(CPUPPCState *env)
+{
+ /* Add a number of P7 book4 registers */
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_kvm(env, SPR_ACOP, "ACOP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_ACOP, 0);
+ spr_register_kvm(env, SPR_BOOKS_PID, "PID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PID, 0);
+#endif
+}
+
static void init_proc_book3s_64(CPUPPCState *env, int version)
{
gen_spr_ne_601(env);
@@ -8066,6 +8081,9 @@ static void init_proc_book3s_64(CPUPPCState *env, int
version)
gen_spr_power6_common(env);
gen_spr_power6_dbg(env);
}
+ if (version == BOOK3S_CPU_POWER7) {
+ gen_spr_power7_book4(env);
+ }
if (version >= BOOK3S_CPU_POWER8) {
gen_spr_power8_tce_address_control(env);
gen_spr_power8_ids(env);
--
2.5.5
- [Qemu-devel] [PULL 14/26] spapr_pci: Drop cannot_instantiate_with_device_add_yet=false, (continued)
- [Qemu-devel] [PULL 14/26] spapr_pci: Drop cannot_instantiate_with_device_add_yet=false, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 12/26] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 04/26] spapr_iommu: Introduce "enabled" state for TCE table, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 06/26] spapr_iommu: Add root memory region, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 20/26] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 24/26] ppc: Fix slbia decode, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 25/26] ppc: Add missing slbfee. instruction on ppc64 BookS processors, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 02/26] kvm: API to obtain max supported mem slots, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 19/26] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 05/26] spapr_iommu: Migrate full state, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 21/26] ppc: POWER7 had ACOP and PID registers,
David Gibson <=
- [Qemu-devel] [PULL 07/26] spapr_pci: Reset DMA config on PHB reset, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 10/26] spapr: Introduce pseries-2.7 machine type, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 26/26] ppc: Do not take exceptions on unknown SPRs in privileged mode, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 08/26] spapr_pci: Add and export DMA resetting helper, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 11/26] ppc: Better figure out if processor has HV mode, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 16/26] macio: use DMA memory interface for non-block ATAPI transfers, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 17/26] dbdma: use DMA memory interface for memory accesses, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 13/26] ppc: fix hrfid, tlbia and slbia privilege, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 22/26] ppc: POWER7 has lq/stq instructions and stq need to check ISA, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 18/26] ppc: Properly tag the translation cache based on MMU mode, David Gibson, 2016/06/07