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[Qemu-devel] [PULL 12/26] ppc: Fix hreg_store_msr() so that non-HV mode
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 12/26] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV |
Date: |
Tue, 7 Jun 2016 20:47:59 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
This helper is only used by the various instructions that can alter
MSR and not interrupts. Add a comment to that effect to the interrupt
code as well in case somebody wants to change this
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/excp_helper.c | 8 ++++++--
target-ppc/helper_regs.h | 4 ++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index a37009e..30e960e 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -709,8 +709,12 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
}
}
#endif
- /* XXX: we don't use hreg_store_msr here as already have treated
- * any special case that could occur. Just store MSR and update hflags
+ /* We don't use hreg_store_msr here as already have treated
+ * any special case that could occur. Just store MSR and update hflags
+ *
+ * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
+ * will prevent setting of the HV bit which some exceptions might need
+ * to do.
*/
env->msr = new_msr & env->msr_mask;
hreg_compute_hflags(env);
diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
index 57da931..12af61c 100644
--- a/target-ppc/helper_regs.h
+++ b/target-ppc/helper_regs.h
@@ -114,8 +114,8 @@ static inline int hreg_store_msr(CPUPPCState *env,
target_ulong value,
excp = 0;
value &= env->msr_mask;
#if !defined(CONFIG_USER_ONLY)
- if (!alter_hv) {
- /* mtmsr cannot alter the hypervisor state */
+ /* Neither mtmsr nor guest state can alter HV */
+ if (!alter_hv || !(env->msr & MSR_HVB)) {
value &= ~MSR_HVB;
value |= env->msr & MSR_HVB;
}
--
2.5.5
- [Qemu-devel] [PULL 00/26] ppc-for-2.7 queue 20160607, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 03/26] vmstate: Define VARRAY with VMS_ALLOC, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 23/26] ppc: Fix mtmsr decoding, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 14/26] spapr_pci: Drop cannot_instantiate_with_device_add_yet=false, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 12/26] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV,
David Gibson <=
- [Qemu-devel] [PULL 04/26] spapr_iommu: Introduce "enabled" state for TCE table, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 06/26] spapr_iommu: Add root memory region, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 20/26] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 24/26] ppc: Fix slbia decode, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 25/26] ppc: Add missing slbfee. instruction on ppc64 BookS processors, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 02/26] kvm: API to obtain max supported mem slots, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 19/26] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 05/26] spapr_iommu: Migrate full state, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 21/26] ppc: POWER7 had ACOP and PID registers, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 07/26] spapr_pci: Reset DMA config on PHB reset, David Gibson, 2016/06/07