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[Qemu-devel] [PULL 24/26] ppc: Fix slbia decode
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 24/26] ppc: Fix slbia decode |
Date: |
Tue, 7 Jun 2016 20:48:11 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
Since at least the 2.05 architecture, the slbia instruction takes an
IH field in the opcode to provide some control on the effect of the
slbia on the ERATs (level-1 TLB).
We can safely ignore it as we always flush the whole qemu TLB but
we should allow the bits in the decode.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c7f5223..0b6a4b6 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9980,7 +9980,7 @@ GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001,
PPC_MEM_TLBIE),
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
-GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
+GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
--
2.5.5
- [Qemu-devel] [PULL 00/26] ppc-for-2.7 queue 20160607, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 03/26] vmstate: Define VARRAY with VMS_ALLOC, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 23/26] ppc: Fix mtmsr decoding, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 14/26] spapr_pci: Drop cannot_instantiate_with_device_add_yet=false, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 12/26] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 04/26] spapr_iommu: Introduce "enabled" state for TCE table, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 06/26] spapr_iommu: Add root memory region, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 20/26] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 24/26] ppc: Fix slbia decode,
David Gibson <=
- [Qemu-devel] [PULL 25/26] ppc: Add missing slbfee. instruction on ppc64 BookS processors, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 02/26] kvm: API to obtain max supported mem slots, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 19/26] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 05/26] spapr_iommu: Migrate full state, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 21/26] ppc: POWER7 had ACOP and PID registers, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 07/26] spapr_pci: Reset DMA config on PHB reset, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 10/26] spapr: Introduce pseries-2.7 machine type, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 26/26] ppc: Do not take exceptions on unknown SPRs in privileged mode, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 08/26] spapr_pci: Add and export DMA resetting helper, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 11/26] ppc: Better figure out if processor has HV mode, David Gibson, 2016/06/07