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[Qemu-devel] [PULL 11/26] ppc: Better figure out if processor has HV mod
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 11/26] ppc: Better figure out if processor has HV mode |
Date: |
Tue, 7 Jun 2016 20:47:58 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
We use an env. flag which is set to the initial value of MSR_HVB in
the msr_mask. We also adjust the POWER8 mask to set SHV.
Also use this to adjust ctx.hv so that it is *set* when the processor
doesn't have an HV mode (970 with Apple mode for example), thus enabling
hypervisor instructions/SPRs.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[clg: ctx.hv used to be defined only for the hypervisor kernel
(HV=1|PR=0). It is now defined also when PR=1 and conditions are
fixed accordingly.
stripped unwanted tabs.]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/cpu.h | 4 ++++
target-ppc/translate.c | 4 +++-
target-ppc/translate_init.c | 19 +++++++++++++++----
3 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 98a24a5..d8f8f7e 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1050,6 +1050,10 @@ struct CPUPPCState {
hwaddr mpic_iack;
/* true when the external proxy facility mode is enabled */
bool mpic_proxy;
+ /* set when the processor has an HV mode, thus HV priv
+ * instructions and SPRs are diallowed if MSR:HV is 0
+ */
+ bool has_hv_mode;
#endif
/* Those resources are used only during code translation */
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 123e42f..c6b74b8 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -11478,8 +11478,10 @@ void gen_intermediate_code(CPUPPCState *env, struct
TranslationBlock *tb)
ctx.exception = POWERPC_EXCP_NONE;
ctx.spr_cb = env->spr_cb;
ctx.pr = msr_pr;
- ctx.hv = !msr_pr && msr_hv;
ctx.mem_idx = env->dmmu_idx;
+#if !defined(CONFIG_USER_ONLY)
+ ctx.hv = msr_hv || !env->has_hv_mode;
+#endif
ctx.insns_flags = env->insns_flags;
ctx.insns_flags2 = env->insns_flags2;
ctx.access_type = -1;
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 8301076..55f8553 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8450,6 +8450,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
PPC2_TM;
pcc->msr_mask = (1ull << MSR_SF) |
+ (1ull << MSR_SHV) |
(1ull << MSR_TM) |
(1ull << MSR_VR) |
(1ull << MSR_VSX) |
@@ -9854,10 +9855,7 @@ static void ppc_cpu_reset(CPUState *s)
pcc->parent_reset(s);
msr = (target_ulong)0;
- if (0) {
- /* XXX: find a suitable condition to enable the hypervisor mode */
- msr |= (target_ulong)MSR_HVB;
- }
+ msr |= (target_ulong)MSR_HVB;
msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
msr |= (target_ulong)1 << MSR_EP;
@@ -9958,6 +9956,19 @@ static void ppc_cpu_initfn(Object *obj)
env->bfd_mach = pcc->bfd_mach;
env->check_pow = pcc->check_pow;
+ /* Mark HV mode as supported if the CPU has an MSR_HV bit
+ * in the msr_mask. The mask can later be cleared by PAPR
+ * mode but the hv mode support will remain, thus enforcing
+ * that we cannot use priv. instructions in guest in PAPR
+ * mode. For 970 we currently simply don't set HV in msr_mask
+ * thus simulating an "Apple mode" 970. If we ever want to
+ * support 970 HV mode, we'll have to add a processor attribute
+ * of some sort.
+ */
+#if !defined(CONFIG_USER_ONLY)
+ env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
+#endif
+
#if defined(TARGET_PPC64)
if (pcc->sps) {
env->sps = *pcc->sps;
--
2.5.5
- [Qemu-devel] [PULL 24/26] ppc: Fix slbia decode, (continued)
- [Qemu-devel] [PULL 24/26] ppc: Fix slbia decode, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 25/26] ppc: Add missing slbfee. instruction on ppc64 BookS processors, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 02/26] kvm: API to obtain max supported mem slots, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 19/26] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 05/26] spapr_iommu: Migrate full state, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 21/26] ppc: POWER7 had ACOP and PID registers, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 07/26] spapr_pci: Reset DMA config on PHB reset, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 10/26] spapr: Introduce pseries-2.7 machine type, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 26/26] ppc: Do not take exceptions on unknown SPRs in privileged mode, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 08/26] spapr_pci: Add and export DMA resetting helper, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 11/26] ppc: Better figure out if processor has HV mode,
David Gibson <=
- [Qemu-devel] [PULL 16/26] macio: use DMA memory interface for non-block ATAPI transfers, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 17/26] dbdma: use DMA memory interface for memory accesses, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 13/26] ppc: fix hrfid, tlbia and slbia privilege, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 22/26] ppc: POWER7 has lq/stq instructions and stq need to check ISA, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 18/26] ppc: Properly tag the translation cache based on MMU mode, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 15/26] target-ppc: fixup bitrot in mmu_helper.c debug statements, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 01/26] target-ppc/fpu_helper: Fix efscmp* instructions handling, David Gibson, 2016/06/07
- [Qemu-devel] [PULL 09/26] spapr: Increase hotpluggable memory slots to 256, David Gibson, 2016/06/07
- Re: [Qemu-devel] [PULL 00/26] ppc-for-2.7 queue 20160607, Peter Maydell, 2016/06/07