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[Qemu-devel] [PULL 17/62] ARM: cpu: add "reset_hivecs" property
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 17/62] ARM: cpu: add "reset_hivecs" property |
Date: |
Tue, 17 Dec 2013 20:28:35 +0000 |
From: Antony Pavlov <address@hidden>
Add an ARM CPU property for the reset value of hivecs as it is a
board/SoC configurable setting.
The existence of the property is conditional on the ARM CPU not being M
class.
Signed-off-by: Antony Pavlov <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
[ PC Changes:
* Elaborated commit message
* refactored to use qdev_property_add_static
]
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 13 +++++++++++++
2 files changed, 14 insertions(+)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index f32178a..afbd422 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -139,6 +139,7 @@ typedef struct ARMCPU {
uint32_t ccsidr[16];
uint32_t reset_cbar;
uint32_t reset_auxcr;
+ bool reset_hivecs;
} ARMCPU;
#define TYPE_AARCH64_CPU "aarch64-cpu"
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index fd04b36..3bce1d6 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -235,6 +235,9 @@ static void arm_cpu_initfn(Object *obj)
static Property arm_cpu_reset_cbar_property =
DEFINE_PROP_UINT32("reset-cbar", ARMCPU, reset_cbar, 0);
+static Property arm_cpu_reset_hivecs_property =
+ DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
+
static void arm_cpu_post_init(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -245,6 +248,12 @@ static void arm_cpu_post_init(Object *obj)
&err);
assert_no_error(err);
}
+
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
+ &err);
+ assert_no_error(err);
+ }
}
static void arm_cpu_finalizefn(Object *obj)
@@ -307,6 +316,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
set_feature(env, ARM_FEATURE_PXN);
}
+ if (cpu->reset_hivecs) {
+ cpu->reset_sctlr |= (1 << 13);
+ }
+
register_cp_regs_for_features(cpu);
arm_cpu_register_gdb_regs_for_features(cpu);
--
1.8.5
- [Qemu-devel] [PULL 21/62] target-arm: Add minimal KVM AArch64 support, (continued)
- [Qemu-devel] [PULL 21/62] target-arm: Add minimal KVM AArch64 support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 07/62] Fix CFI query responses for NOR flash, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 14/62] arm/xilinx_zynq: Use object_new() rather than cpu_arm_init(), Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 04/62] return status for each NOR flash device, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 12/62] arm/highbank: Use object_new() rather than cpu_arm_init(), Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 05/62] Set proper device-width for vexpress flash, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 60/62] hw/arm: add allwinner a10 SoC support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 18/62] ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 11/62] target-arm/cpu: Convert reset CBAR to a property, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 20/62] target-arm: Clean up handling of AArch64 PSTATE, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 17/62] ARM: cpu: add "reset_hivecs" property,
Peter Maydell <=
- [Qemu-devel] [PULL 09/62] target-arm/helper.c: Allow cp15.c15 dummy override, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 06/62] Add max device width parameter for NOR devices, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 01/62] target-arm: add support for v8 AES instructions, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 19/62] target-arm/kvm: Split 32 bit only code into its own file, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 57/62] vmstate: Add support for an array of ptimer_state *, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 34/62] target-arm: A64: add support for BR, BLR and RET insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 35/62] target-arm: A64: add support for conditional branches, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 16/62] arm/highbank.c: Fix MPCore periphbase name, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 32/62] target-arm: A64: expand decoding skeleton for system instructions, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 28/62] target-arm: A64: provide functions for accessing FPCR and FPSR, Peter Maydell, 2013/12/17