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[Qemu-devel] [PULL 34/62] target-arm: A64: add support for BR, BLR and R
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 34/62] target-arm: A64: add support for BR, BLR and RET insns |
Date: |
Tue, 17 Dec 2013 20:28:52 +0000 |
From: Alexander Graf <address@hidden>
Implement BR, BLR and RET. This is all of the 'unconditional
branch (register)' instruction category except for ERET
and DPRS (which are system mode only).
Signed-off-by: Alexander Graf <address@hidden>
[claudio: reimplemented on top of new decoder structure]
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 43 +++++++++++++++++++++++++++++++++++++++++--
1 file changed, 41 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index ead5658..b694665 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -384,10 +384,49 @@ static void disas_exc(DisasContext *s, uint32_t insn)
unsupported_encoding(s, insn);
}
-/* Unconditional branch (register) */
+/* C3.2.7 Unconditional branch (register)
+ * 31 25 24 21 20 16 15 10 9 5 4 0
+ * +---------------+-------+-------+-------+------+-------+
+ * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
+ * +---------------+-------+-------+-------+------+-------+
+ */
static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
+ unsigned int opc, op2, op3, rn, op4;
+
+ opc = extract32(insn, 21, 4);
+ op2 = extract32(insn, 16, 5);
+ op3 = extract32(insn, 10, 6);
+ rn = extract32(insn, 5, 5);
+ op4 = extract32(insn, 0, 5);
+
+ if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ switch (opc) {
+ case 0: /* BR */
+ case 2: /* RET */
+ break;
+ case 1: /* BLR */
+ tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
+ break;
+ case 4: /* ERET */
+ case 5: /* DRPS */
+ if (rn != 0x1f) {
+ unallocated_encoding(s);
+ } else {
+ unsupported_encoding(s, insn);
+ }
+ return;
+ default:
+ unallocated_encoding(s);
+ return;
+ }
+
+ tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
+ s->is_jmp = DISAS_JUMP;
}
/* C3.2 Branches, exception generating and system instructions */
--
1.8.5
- [Qemu-devel] [PULL 60/62] hw/arm: add allwinner a10 SoC support, (continued)
- [Qemu-devel] [PULL 60/62] hw/arm: add allwinner a10 SoC support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 18/62] ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 11/62] target-arm/cpu: Convert reset CBAR to a property, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 20/62] target-arm: Clean up handling of AArch64 PSTATE, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 17/62] ARM: cpu: add "reset_hivecs" property, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 09/62] target-arm/helper.c: Allow cp15.c15 dummy override, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 06/62] Add max device width parameter for NOR devices, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 01/62] target-arm: add support for v8 AES instructions, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 19/62] target-arm/kvm: Split 32 bit only code into its own file, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 57/62] vmstate: Add support for an array of ptimer_state *, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 34/62] target-arm: A64: add support for BR, BLR and RET insns,
Peter Maydell <=
- [Qemu-devel] [PULL 35/62] target-arm: A64: add support for conditional branches, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 16/62] arm/highbank.c: Fix MPCore periphbase name, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 32/62] target-arm: A64: expand decoding skeleton for system instructions, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 28/62] target-arm: A64: provide functions for accessing FPCR and FPSR, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 25/62] default-configs: Add config for aarch64-softmmu, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 27/62] target-arm: A64: add set_pc cpu method, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 33/62] target-arm: A64: add support for B and BL insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 31/62] target-arm: A64: provide skeleton for a64 insn decoding, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 30/62] target-arm: A64: add stubs for a64 specific helpers, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 29/62] target-arm: Support fp registers in gdb stub, Peter Maydell, 2013/12/17