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[Qemu-devel] [PULL 16/62] arm/highbank.c: Fix MPCore periphbase name
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 16/62] arm/highbank.c: Fix MPCore periphbase name |
Date: |
Tue, 17 Dec 2013 20:28:34 +0000 |
From: Peter Crosthwaite <address@hidden>
GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
code that this is the base address of the MPCore. Rename to
MPCORE_PERIPHBASE accordingly.
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/highbank.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index cb32325..c75b425 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -28,11 +28,11 @@
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
-#define SMP_BOOT_ADDR 0x100
-#define SMP_BOOT_REG 0x40
-#define GIC_BASE_ADDR 0xfff10000
+#define SMP_BOOT_ADDR 0x100
+#define SMP_BOOT_REG 0x40
+#define MPCORE_PERIPHBASE 0xfff10000
-#define NIRQ_GIC 160
+#define NIRQ_GIC 160
/* Board init. */
@@ -55,7 +55,7 @@ static void hb_write_secondary(ARMCPU *cpu, const struct
arm_boot_info *info)
0xe1110001, /* tst r1, r1 */
0x0afffffb, /* beq <wfi> */
0xe12fff11, /* bx r1 */
- GIC_BASE_ADDR /* privbase: gic address. */
+ MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */
};
for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
smpboot[n] = tswap32(smpboot[n]);
@@ -236,7 +236,8 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum
cxmachines machine)
cpu = ARM_CPU(object_new(object_class_get_name(oc)));
- object_property_set_int(OBJECT(cpu), GIC_BASE_ADDR, "reset-cbar",
&err);
+ object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
+ &err);
if (err) {
error_report("%s", error_get_pretty(err));
exit(1);
@@ -287,7 +288,7 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum
cxmachines machine)
qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
- sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
+ sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
for (n = 0; n < smp_cpus; n++) {
sysbus_connect_irq(busdev, n, cpu_irq[n]);
}
--
1.8.5
- [Qemu-devel] [PULL 11/62] target-arm/cpu: Convert reset CBAR to a property, (continued)
- [Qemu-devel] [PULL 11/62] target-arm/cpu: Convert reset CBAR to a property, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 20/62] target-arm: Clean up handling of AArch64 PSTATE, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 17/62] ARM: cpu: add "reset_hivecs" property, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 09/62] target-arm/helper.c: Allow cp15.c15 dummy override, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 06/62] Add max device width parameter for NOR devices, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 01/62] target-arm: add support for v8 AES instructions, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 19/62] target-arm/kvm: Split 32 bit only code into its own file, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 57/62] vmstate: Add support for an array of ptimer_state *, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 34/62] target-arm: A64: add support for BR, BLR and RET insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 35/62] target-arm: A64: add support for conditional branches, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 16/62] arm/highbank.c: Fix MPCore periphbase name,
Peter Maydell <=
- [Qemu-devel] [PULL 32/62] target-arm: A64: expand decoding skeleton for system instructions, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 28/62] target-arm: A64: provide functions for accessing FPCR and FPSR, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 25/62] default-configs: Add config for aarch64-softmmu, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 27/62] target-arm: A64: add set_pc cpu method, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 33/62] target-arm: A64: add support for B and BL insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 31/62] target-arm: A64: provide skeleton for a64 insn decoding, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 30/62] target-arm: A64: add stubs for a64 specific helpers, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 29/62] target-arm: Support fp registers in gdb stub, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 15/62] arm/xilinx_zynq: Implement CBAR initialisation, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 61/62] hw/arm: add cubieboard support, Peter Maydell, 2013/12/17