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Re: softmmu 'at' instruction support

From: Peter Maydell
Subject: Re: softmmu 'at' instruction support
Date: Fri, 19 Nov 2021 15:59:24 +0000

On Fri, 19 Nov 2021 at 14:39, Janne Karhunen <janne.karhunen@gmail.com> wrote:
> On Fri, Nov 19, 2021 at 4:28 PM Peter Maydell <peter.maydell@linaro.org> 
> wrote:
> > Note also that not all ELs have two TTBRs; some have only TTBR0,
> > in which case you get figure D5-2, with just the starting-from-0
> > part of the address space being valid.
> >
> > Big question: I thought we were talking about doing lookups
> > on virtual address 0 here? That should be using TTBR0, so why
> > do you expect it to be using TTBR1?
> I suppose I wasn't entirely clear on the kernel/user mapping split, I
> just did the second stage and didn't really care about what exactly
> happens in the guest. Things seemed to be a bit more complicated than
> I thought as bits above 48/52 were not ignored after all and made all
> the difference on the table selection. I had the impression it was
> just the calling context that defined the table to be used.

Calling context defines the "translation regime" to be used;
some translation regimes support having two virtual address
ranges and thus two TTBRx registers. (The usual approach at
the OS level is that you make TTBR0_EL1 cover the userspace
process's mappings and TTBR1_EL1 cover the kernel's mappings,
so you can switch processes by changing TTBR0_EL1 only and
leaving the kernel mappings as-is; but that's not obligatory.)

-- PMM

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