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Re: softmmu 'at' instruction support

From: Peter Maydell
Subject: Re: softmmu 'at' instruction support
Date: Thu, 18 Nov 2021 11:41:14 +0000

On Thu, 18 Nov 2021 at 09:09, Janne Karhunen <janne.karhunen@gmail.com> wrote:
> This looks like a bug to me, please comment if I'm wrong:

Bit hard to say without a reproduce case... You also don't
say what QEMU version you're using.

> 0x0000000100004a3c <at_s12e1r+8>: 80 78 0c d5 at s12e1r, x0
> 0x0000000100004a40 <at_s12e1r+12>: 01 74 38 d5 mrs x1, par_el1
> (gdb) info registers x0 x1
> x0             0x0                 0
> x1             0x809               2057
> So that would be translation fault level 0, stage 1 if I'm not mistaken.

If you want to walk through what QEMU does and why it
returns the fault indication, you can run QEMU under
a debugger and put a breakpoint at ats_write64().
That will do the page table walk (in get_phys_addr())
and you can see where and why we decide that it should
report a fault to the PAR_EL1.

-- PMM

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