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Re: [Qemu-devel] [PATCH v3 07/13] target/mips: Add emulation of MMI inst


From: Richard Henderson
Subject: Re: [Qemu-devel] [PATCH v3 07/13] target/mips: Add emulation of MMI instruction PEXEW
Date: Tue, 5 Mar 2019 04:32:57 -0800
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0

On 3/4/19 7:13 AM, Mateja Marjanovic wrote:
> +    } else {
> +        TCGv_i64 t0 = tcg_temp_new();
> +        TCGv_i64 t1 = tcg_temp_new();
> +        TCGv_i64 t2 = tcg_temp_new();
> +        uint64_t mask0 = (1ULL << 32) - 1;
> +        uint64_t mask1 = mask0 << 32;
> +
> +        tcg_gen_movi_i64(t1, 0);
> +        tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
> +        tcg_gen_or_i64(t1, t0, t1);
> +        tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
> +        tcg_gen_shri_i64(t0, t0, 64);

This line should abort, since the shift count is out of range.
Are you testing with --enable-debug-tcg?

> +        tcg_gen_or_i64(t1, t0, t1);
> +        tcg_gen_mov_i64(t2, t1);

But again, this whole thing is two deposit operations:

    tcg_gen_mov_i64(t0, cpu_gpr[rt]);
    tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_mmr[rt], 0, 32);
    tcg_gen_deposit_i64(cpu_mmr[rd], cpu_mmr[rt], t0, 0, 32);


r~



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